Introduction to Analog Devices Blackfin Processors

During the past decade, industrial control and instrumentation applications have seen a steady increase in the adoption of analog and digital technologies, a trend that doesn’t seem to be slowing. What is clear is that in order to keep pace with the market’s package and application level demands, highly efficient technologies are needed to support the continuing evolution of industrial control and instrumentation designs. Analog Devices Blackfin® processors offer best-in-class performance for the given power and cost, allowing developers to create intelligently aware systems that communicate via wireless or wired connections and are not limited to a specific package or standard.

Common Applications

Industrial Power Control

• Communication, control, and intelligent sensing
• UPS/Power supplies
• Motion/motor control/drives

Test and Measurement

• Science and lab test equipment
• Handheld/battery-powered systems
• Flow and energy
• High speed signal processing enhancements

Blackfin Features

The feature-rich Blackfin Processor family is ideally suited for a wide range of industrial applications, from low power metering to high end networked power control systems. With models spanning from low cost to the highest performance with pin- and code-compatible models, designers can choose a device that has been optimized for their industrial application. Code leveragability and Lockbox™ Secure Technology reduce time to market, add flexibility, and safeguard your code. The powerful, scalable, software-programmable 16-/32-bit embedded architecture blends microcontroller unit (MCU) and digital signal processing (DSP) capabilities onto a single chip, eliminating the need for a multiprocessor approach. With applications-tuned peripherals including CAN 2.0B, PWM outputs, TWIs, 10/100 Ethernet, SPORTs, UARTs, PPIs, and GPIOs, designers have all the flexibility they need.

Blackfin Processors offer performance up to 750 MHz/1512 MMACS in single-core products. New symmetric, multiprocessor members of the Blackfin family extend this to over 3000 MMACS. The family offers the lowest power consumption—as low as 0.15 mW/MMAC at 0.8 V. The combination of high performance and low power is essential in meeting the needs of signal processing applications today and in the future— including broadband wireless, audio/video-capable Internet appliances, and mobile communications.

Blackfin Architecture

• Single instruction-set architecture with processing performance that meets or beats the competition's DSP product range - and provides better power, cost, and memory efficiency.
• 16/32-bit architecture enables next generation embedded applications.
• Control, signal, and multimedia processing in a single core.
• Performance tunable for signal processing or power consumption through dynamic power management.
• Portfolio of code- and pin-compatible products. Under $5 to 1,500 MIPS - leverages engineering development across a wide range of end products.
• Twice the performance and half the power of competing DSPs*, enabling breakthrough specs and new applications.
• Quickly adopted into thousands of designs, supported by multiple tool chains and operating systems.
• Increases developer productivity.
• Minimal optimization required due to powerful software development environment coupled with core performance.
• Extensive third party ecosystem mitigates risk.
• Supported by industry-leading development tools, RTOS, software providers, and system integration partners.

General purpose register files

The Blackfin Processor core includes an 8-entry by 32-bit data register file for general use by the computational units. Supported data types include 8-, 16-, or 32-bit signed or unsigned integer and 16- or 32-bit signed fractional. In every clock cycle, this multiported register file supports two 32-bit reads AND two 32-bit writes. It can also be accessed as a 16-entry by 16-bit data register file.

The address register file provides a general purpose addressing mechanism in addition to supporting circular buffering and stack maintenance. This register file consists of 8 entries and includes a frame pointer and a stack pointer. The frame pointer is useful for subroutine parameter passing, while the stack pointer is useful for storing the return address from subroutine calls.

Data Arithmetic Unit

The Data Arithmetic Unit contains roughly twice the system resources of previous Analog Devices 16-bit architectures. It contains:

• Two 16-bit MACs
• Two 40-bit ALUs
• Four 8-bit video ALUs
• Single barrel shifter

All computational resources can process 8-, 16-, or 32-bit operands from the data register file-R0 through R7. Each register can be accessed as a 32-bit register or a 16-bit register high or low half.

In a single clock cycle, this SIMD architecture can read AND write up to two 32-bit values. However, since the high and low halves of the R0 through R7 registers are individually addressable (Rx, Rx.H, or Rx.L), each computational block can choose from either two 32-bit input values or four 16-bit input values with no restrictions on input data. The results of the computation can be written back into the register file as either a 32-bit entity or as the high or low 16-bit half of the register. Additionally, the method of accumulation can vary between data paths. For example, A0 could be a constant summation, and A1 could be a constant subtraction. This capability is referred to as 'flexible SIMD'.

Both accumulators are 40 bits in length, providing 8 bits of extended precision. Similar to the general purpose registers, both accumulators can be accessed in 16-, 32-, or 40-bit increments. The Blackfin architecture also supports a combined add/subtract instruction that can generate two 16-, 32-, or 40-bit results or four 16-bit results. In the case where four 16-bit results are desired, the high and low half results can be interchanged. This is a very powerful capability and significantly improves, for instance, the FFT benchmark results.

Address Arithmetic Unit

Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from memory. The DAGs share a register file that contains four sets of 32-bit index (I), length(L), base(B), and modify(M) registers. There are also eight additional 32-bit address registers—P0 through P5, frame pointer, and stack pointer—that can be used as pointers for general indexing of variables and stack locations.

The four sets of I, L, B, and M registers are useful for implementing circular buffering. Used together, each set of index, length, and base registers can implement a unique circular buffer in internal or external memory. The Blackfin architecture also supports a variety of addressing modes, including indirect, autoincrement and decrement, indexed, and bit reversed. Last, all address registers are 32 bits in length, supporting the full 4 Gbyte address range of the Blackfin Processor architecture.

Program sequencer unit

The program sequencer controls the flow of instruction execution and supports conditional jumps and subroutine calls, as well as nested zero-overhead looping. A multistage fully interlocked pipeline guarantees code is executed as expected and that all data hazards are hidden from the programmer. This type of pipeline guarantees result accuracy by stalling when necessary to achieve proper results. This greatly simplifies the programming task since the software engineer doesn't have to completely understand pipeline latency issues. On-chip interlocking hardware ensures that operand data is valid at the time of a particular instruction's execution.

The Blackfin architecture supports 16- and 32-bit instruction lengths in addition to limited multi-issue 64-bit instruction packets. This ensures maximum code density by encoding the most frequently used control instructions as compact 16-bit words and the more challenging math operations as 32-bit double words.

For More Information:

View the Blackfin Selection Table

Learn more about the LabVIEW Embedded Module for Blackfin Processors

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