Importing External IP into LabVIEW FPGA with the CLIP Node

The Component-Level Intellectual Property (CLIP) Node is a framework for importing external field-programmable gate array intellectual property (FPGA IP) into the NI LabVIEW FPGA Module. This document examines CLIP Node usage and offers a video tutorial for each step of the process.

Introduction

The CLIP Node is a framework for importing existing FPGA IP into LabVIEW FPGA hardware and communicating to it through the LabVIEW FPGA diagram. The IP can be in the form of direct VHDL or intermediate files like EDIF netlists.

User-defined CLIP − Enables VHDL code to communicate directly with an FPGA VI.

Socketed CLIP − Enables VHDL code to communicate directly with an FPGA VI and FPGA pins that are not exposed to the LabVIEW FPGA Module. Some FPGA targets define a fixed CLIP socket in the FPGA where you can insert socketed CLIP.

In general, this feature targets users with some digital design experience, general knowledge of VHDL, and a working understanding of XML. This document examines CLIP usage and provides a step-by step video tutorial of a particular function, from VHDL to final implementation. For the most up-to-date information, always refer to the help topic in the LabVIEW FPGA Module Help titled “Using VHDL Code as Component-Level IP (FPGA Module).” This document is listed in this paper several times as a resource for more information.

CLIP Node versus HDL Node

There has always been a feature for importing existing VHDL into LabVIEW FPGA using the HDL Node. However, the HDL Node has several limitations that are solved using the CLIP Node. The high-level difference between the two nodes is that the HDL Node requires that the logic fit into the under-the-hood dataflow paradigm of LabVIEW FPGA. Often, this requires you to fully understand how LabVIEW is converted to hardware and how to use the associated synchronization logic and “enable chain.” In some cases, this also requires edits to the IP. With the CLIP Node, you have a more black-box approach to importing IP so that no code changes are typically needed and you can literally instantiate almost anything you can use on other FPGA platforms. In addition to the difference in dataflow execution, the CLIP Node goes beyond the HDL Node by helping you:

• Run VHDL code in parallel with LabVIEW code
• Execute VHDL code in multiple clock domains
• Include constraints in the compilation
• Communicate directly to I/O pins on some hardware

Five Steps for Integrating IP with CLIP 

1. Create or acquire the IP
2. Define the interface to the IP using a declaration XML file (Try the CLIP XML Wizard)
3. Declare CLIP in the properties of an FPGA target
4. Add a CLIP item to a LabVIEW Project
5. Pass data between CLIP and an FPGA VI

For each step in this process, the document discusses the step and uses a video example to further explain the concept. Consider the example of a discrete cosine transform (DCT) implementation created by a user on Opencores.org. The DCT is similar to the Fourier transform and is most often used for data compression. In fact, DCT is a standard block of JPEG and MPEG.

1. Create or Acquire the IP

You can reuse FPGA IP from any source in CLIP. If you have VHDL (or other digital design) experience, you can certainly write code to import through CLIP. However, you typically need CLIP to import existing IP. This IP might be previously written internal code or acquired from a third party. Because NI uses Xilinx FPGAs and the Xilinx toolchain in LabVIEW FPGA, you can easily use the Xilinx CORE Generator to create compatible cores. Also, you can use the Xilinx Embedded Development Kit (EDK) to create any flavor of soft microprocessor. There are also many third-party IP vendors that can provide all types of signal processing, bus solutions, or application-specific cores.

You can write the IP acquired in VHDL directly or import it through netlist files. To take advantage of other hardware description languages like Verilog, use the Xilinx tools to create a netlist out of the Verilog code first. As you begin the process of using CLIP, you need to keep in mind a few considerations, especially that you are limited to only a few data types for passing data.

Table 1. Legal Data Types You Can Use in the CLIP Interface

If your IP uses a logic vector that is not one of these data types, you need to write a VHDL wrapper to extend, cut off, or break up the standard LabVIEW types to fit the data widths of the IP. Refer to the example tutorial to learn how to use a VHDL wrapper to extend a 12-bit number to 16 bits for use in LabVIEW. Additionally, refer to the LabVIEW FPGA Module Help to understand other considerations for your IP including using external clocks, crossing clock domains, using synchronization registers, implementing asynchronous resets, and working with constraints and hierarchy. 

2. Define the Interface to the IP Using a Declaration XML File

To map the IP inputs and outputs to I/O in LabVIEW, create an XML that defines the necessary characteristics of the IP. The beginning of the XML file starts with the CLIP declaration tag and some other standard code:

<?xml version="1.0"?>
<CLIPDeclaration Name="My VHDL IP">
<FormatVersion>1.0</FormatVersion>
<HDLName>MY_IP</HDLName>
</CLIPDeclaration>>/p>

Figure 1. Typical Header Information for an XML Interface File for CLIP 

After the header, use the <Implementation List> and <Path> tags to define the directory(ies) containing all the VHDL source code. Finally, use the <Interface List> with all of the other tags to define each signal type, signal name, HDL name, signal data type, directionality, and other attributes of the inputs and outputs of CLIP. The Help file has a detailed chart of each tag, usage guidelines, and an example of a simple CLIP XML file. Also, try the CLIP XML Wizard to automatically create an XML description from the top level VHDL file. 

3. Declare the CLIP in the Properties of an FPGA Target

Once you create an XML file to define the LabVIEW interface to the IP, you must declare the CLIP in the project. To do this, right-click the FPGA target and select Properties. The Properties dialog contains a section labeled “Component-Level IP.” Press the “add” button to declare a CLIP function and select the XML file from the browse dialog.

Figure 2. This dialog appears when you declare the CLIP Node on the FPGA target. Use the “add” button to browse to the desired XML file.

Once you have declared the CLIP by selecting the XML file, the CLIP declaration name (defined in the XML file) appears alongside the path of the file. In this dialog, you can declare multiple CLIP nodes for all the different IP blocks you need to import.

Note: The button that looks like circular arrows is to “rescan.” Press this when you have changed the XML after declaration.

4. Add a CLIP Item to a LabVIEW Project

Declaring the CLIP within the FPGA does not actually add it to the project. Adding to the project is a separate step because you can actually instantiate multiple instances of one CLIP on the same FPGA. Therefore, once you have the CLIP linked up to the XML file, right-click the FPGA target and select New>>Component-Level IP. You then receive a dialog to select the desired CLIP, give this instance a unique name, and select clocks to connect to any lines in the CLIP with the “Clock” signal type.

Figure 3. This dialog appears when you add an instance of a CLIP to the project. Select the CLIP, define a name, and configure clocks.

Once you press OK from this dialog, this CLIP and all associated inputs and outputs show up in the project in an entry labeled with the instance name.

Figure 4. Project after Adding the CLIP Showing All of the I/O Point for the IP

5. Pass Data between the CLIP and an FPGA VI

At this point, you are ready to communicate between the CLIP and the FPGA VI. To do so, simply drag and drop the desired I/O point from the project to the FPGA diagram. Your IP should have documentation on how to use the IP. For instance, many IP blocks use some type of handshaking lines for passing data in and out. These are typically labeled “data valid” or “enable.” Use LabVIEW logic to send the correct values at the correct times to exercise the IP. You can place CLIP I/O inside or outside a single-cycle timed loop (SCTL), but keep in mind that inside an SCTL, you might have to consider clock domain crossings and use synchronization registers.

[+] Enlarge Image

Figure 5. A Complete Diagram Exercising the CLIP through the Input/Output Node in the Middle of the Diagram

Conclusion

The CLIP Node is a very powerful feature that allows any type of FPGA IP to be pulled into the LabVIEW FPGA context. This is also an important feature for keeping LabVIEW an open language that can accept all types of inputs. Try the five steps using the tutorial in the FPGA Help file to get a simple “hello world” experience around the CLIP. Also, download the files below to get an example of using the DCT (shown in the videos) IP in a CLIP.

Related Links

On-Demand Training: Importing External Codes to LabVIEW FPGA Using CLIP (SSP Required)

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