LabVIEW FPGA Compilation Process: From Run Button to Bitfile

The field-programmable gate array (FPGA) compile process can take a significant amount of time during FPGA development. Whether or not you use NI LabVIEW software, FPGA compile times can last minutes to hours and require some amount of creativity and planning to schedule different work hours, take your lunch, or go home for the day during that time. One technique is to do more simulation on the development computer to avoid unnecessary compiles due to programming errors, but, in the end, compiling and testing in hardware are necessities. This white paper discusses the LabVIEW features and techniques you can use to view alerts about overmapping and timing errors earlier in the compile, queue compiles, implement remote compile servers, and other pertinent information on the significant time spent between kicking off a compile and receiving a working bitfile.

The Full Compile Process

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Figure 1. The Compile Process from Run Arrow to Bitfile

Each step of the compile process has some subtleties and information you can use. NI works to expose this information in a timely manner. You can use NI LabVIEW software to both automatically and manually stop the compilation at any time due to an error, an estimate out of bounds, or a user-directed cancel.

Setting Compile Options before You Start

You can use compiler settings to increase or decrease the effort settings of the compile. The different “Design Strategy” settings are useful in a number of situations including the following. Note that the default setting for the hardware selected is “Balanced” (Figure 2).

1. If you are afraid of overmapping resource usage but you can easily meet timing constraints, choose "Area.”
2. If resource usage is well within your bounds but you are approaching a high clock rate, choose “Timing Performance.”
3. If you are writing an FPGA program that does not stretch resource or timing constraints, choose “Minimum Compile Time.”
4. If you want to customize the effort levels across each dimension, choose “Custom.”

Figure 2. With the Xilinx Options property dialog, you can set the compile effort level before compiling.

A note for FlexRIO users

In addition to compiling user FPGA code, LabVIEW FPGA must also include any FlexRIO Socketed CLIP and a small amount of fixed logic. In order to ensure that all of the extra logic meets timing and space requirements, all effort levels set to "High" by default. Changing these settings could cause a user compile to fail due to non user-generated code, or they could simply result in undesired behavior in user-generated code. Because of this, effort level settings are disabled for all FlexRIO targets.

Starting a Compile

You can choose from several ways to begin compiling an FPGA VI in LabVIEW.

1. The Run Arrow method first checks to see if there is a valid bitfile already created for the VI. If so, it immediately runs the FPGA VI in interactive mode using the existing bitfile. If the FPGA VI has never been compiled or has changed since the last compile, the run arrow begins the compile process and runs in interactive mode after the compile is finished.
2. Holding <Ctrl> and hitting the Run Arrow key compiles the VI without running after finished.
3. Right-clicking the VI in the project»Compile… forces a compile. This method compiles a VI no matter which state the current bitfile is in. It does not begin running when the compile is finished

Generating Intermediate Files

The first step in the compilation process is the generation of intermediate files. For this process, LabVIEW parses your block diagram and converts the code to a form the Xilinx compiler can consume. A number of errors can occur during this step, causing the compile to fail. These errors usually involve an illegal VI or combination of VIs placed in single-cycle loops.

Figure 3. The Generating Intermediate Files Progress Dialog

Figure 4. Example of Errors from Code Generation

Compilation Status Window

After code generation completes with no errors, the Compilation Status window appears. This is the main window that guides you through the compile. It features a progress bar and some basic timestamps and VI info. As the compile continues, alerts at the bottom of the window tell you when a new report is done. After the “Synthesis” step, you see “Estimated Device Utilization” and “Estimated Timing” reports. Both of these reports come early in the compile so you can cancel the compile in a timely fashion if the reports indicate with high confidence that the compile will overmap your FPGA hardware or not meet your timing constraints.

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Figure 5. The Compilation Status window is a dynamic interface that you can use to check various reports, minimize to the progress-only view, and continue working in LabVIEW.

Compilation Status Window Features

• Progress bar output
• Report covering Xilinx precompile options selected
• Clickable alerts when the early estimates (and other reports) are ready to view
• Progress-only view to put the compiler status in the corner of the screen and continue working
• Ability to inspect the raw Xilinx log directly
• “Save” button to quickly save the Xilinx log or particular reports to a file for records or support
• Ability to stop the LabVIEW FPGA Compile Server remotely

Queuing Compiles

To more efficiently use the LabVIEW FPGA Compile Server, you can queue several compiles to run one after another. You can leave the compile server running for an extended period (for example, overnight) or at least make sure that it is busy working as much as possible. Queuing a compile is as simple as kicking off the next compile before the previous compile is finished. To do this, disconnect from the current compile and start the new one. The Compilation Status window for that compile reflects that the compile is waiting in queue above the progress bar.

Figure 6. The Compilation Status window shows that the compile is waiting in queue for the compile server to become available.

You can use the Compile Server window to view all of the compiles waiting in the queue by pressing the Compile List… button in the Compile Server window. If you disconnect from a compile and want to check on its status, right-click on the VI in the project and select Reconnect to Compilation…

Using a Remote Compile Server

By default, the LabVIEW FPGA Compile Server is set to “localhost.” It opens the Compile Server window when the Compilation Status window appears. FPGA compilation is a computationally intensive process and can tax both the processor and RAM of the development machine, making it difficult to continue working on some computers while the compilation is running in the background. Many FPGA developers choose to use a separate PC to run the LabVIEW FPGA Compile Server, and, to optimize compile time, they max out the RAM and processor of this machine. 

Figure 7. The LabVIEW FPGA Compile Server Window

Compiling on a Remote Computer

To choose a remote LabVIEW FPGA Compile Server, select Tools»FPGA Module Options to display the FPGA Module Options dialog box. Enter the name or IP address of the remote computer running the LabVIEW FPGA Compile Server. Depending on the network, you also may need to increase the network timeout.

Figure 8. Use the FPGA Module Options dialog box to set the compile server IP address for a remote machine.

Prior to compiling on a remote computer, you must manually launch the LabVIEW FPGA Compile Server on the remote computer by selecting Start»All Programs»National Instruments»LabVIEW»LabVIEW FPGA Utilities»Compile Server.

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