I2S Communication Reference Application

This tutorial shows how to encode and decode I2S data in LabVIEW. Physical implementations and recommended hardware are also discussed.

Description of I²S

The "Inter IC Sound" (I²S) format is used to transfer serial data between sound ICs.  The I²S bus consists of three lines:

Serial Clock - Typical clock is 2.5MHz
Word Select Line [WS] - Word select indicates which channel is being transmitted; Channel 1 WS = 0 (left), channel 2 WS = 1 (right)
Serial Data Line [SD] - Data transmitted two's complement, MSB first

For more information on I²S, including timing diagrams, please refer to the specifications found at http://www.nxp.com/acrobat_download/various/I2SBUS.pdf.

I²S Encode Decode Program

The I2S_Encode_Decode program can be downloaded by clicking the link at the bottom of this document.  This program shows how to generate I²S data from an array of left and right channel analog samples and then how to convert this I²S data back to left and right channel analog data.

There are three main parts to the I2S_Encode_Decode program:

1)      Generating left and right channel analog data
2)      Converting the left and right channel analog data to I²S data
3)      Converting the I²S data to left and right channel analog data

Generating Left and Right Channel Analog Data

I2S_GenerateAnalogData.vi generates a sine wave for left channel data and an inverse sine wave for right channel data.  The resolution and number of samples for each channel are set by the user.  An example of this generated data is seen below in Figure 1.  When using the I²S VIs to create data for a specific application, replace the data generation step with data specific to the application.

Figure 1. Generated Data for the I²S Encode/Decode Example

Converting the Left and Right Channel Analog Data to I²S data

When encoding I²S data, the user can chose to generate the Master clock, Serial clock, Word Select, and (or) Serial data signals.  These signals are all part of the I²S specification with the exception of the master clock.  The master clock is an optional signal which can be used to provide an over-sampled clock to the I²S chip.  Guidelines for selecting which signals to generate are found in the Table 1 below.

Table 1. How to Choose Which I²S Signals to Generate

As seen in the I²S specification, I²S data alternates between left and right samples.  Because of this behavior, it makes sense to process a single analog sample alternating between left and right data.  In order to process the data more efficiently, several calculations are made and arrays are pre-allocated before the conversion starts.  Figure 2 shows the block diagram of I2S_Encode.vi.  The left most VI pre-allocates arrays.  The two VIs in for loop convert a single analog sample, one left and the other right.

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Figure 2. Block Diagram of I2S_Encode.vi

As mentioned above, the conversion process alternates between left and right analog samples.  The flow chart below shows how these analog samples are converted to I²S data.

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Figure 3. Flow Chart of the Analog Data to I²S Data Conversion

After the conversion is finished, the resulting waveform will look similar to Figure 4.  This is assuming all four signals are generated.  Notice the master clock is running at four times the rate of the serial clock.  If the serial clock is to run at rate x, the digital board must run at 8x.  The reason for this is the master clock should be written low and then high for each clock cycle.  If the digital board were run at the 4x the desired serial clock rate, the resulting waveform would be at half the desired speed.  Applying this concept to a similar situation, if the master clock were omitted, the digital board would need to run at twice the desired serial clock rate.  

Figure 4. Example of an I²S Waveform

Converting the I²S data to Left and Right Analog Data

There are three steps used to decode I²S data:

1)  Removing over-sampling
2)  Converting the I²S data into 2D arrays of left and right data
3)  Converting the left and right 2D arrays into an array of left and right analog samples

Removing Over-Sampling

When the serial clock is used to sample the I²S data, each acquired sample will be unique.  On the other hand, if the master clock or other over-sampled clock is used to acquire the I²S data, the acquired data will contain multiple samples of the same I²S data bit.

Figure 5 shows an I²S waveform sampled using a master clock which is running at twice the rate of the serial clock.  Notice the serial clock is sampled twice, once high and once low, for each data bit.  Since I²S data is only sampled on the rising edge of the clock, there are twice the expected number of samples.  If the data was acquired correctly, there would only be one sample per data bit.

Figure 5. I²S Data Acquired Using a 2x Over-Sampled Master Clock

I2S_RemoveDataOversampling.vi eliminates the over-sampling issue by resampling the data using the rising edge of the Serial Clock.  The resulting waveform is shown below in Figure 6.  Please note, if the data was acquired using the Serial Clock, this step is unnecessary as the data was not over-sampled.

Figure 6. Data after Removing Over-Sampling

Converting the I²S data into 2D arrays of left and right components

The I2S_Decode_Formated_Data.vi decodes I²S data which is not over-sampled.  This means the data was acquired using the Serial Clock or I2S_RemoveDataOversampling.vi was used to remove over-sampling.

As seen in the I²S specifications, when the word select bit changes the next sample is the least significant bit (LSB) of the current analog sample.  This I²S sample is followed by the most significant bit (MSB) of the next left/right analog sample.  See Figure 6 for an illustration.

The concept explained above is used by I2S_Decode_Formated_Data.vi to decode the I²S data.  First an I²S data bit is read.  Depending on the state of the word select line the data bit is added to the corresponding left or right data array.  The next bit is read and added to the next free column of that array.  This process continues until the sample after the word select line changes.  At this time, the current row of the 2D array is finished and the new data is written to the next free row of the 2-D left or right analog array.  After all the I²S data is read, the resulting 2D arrays have the format shown in Table 2 below.

Table 2.  Format of the Left 2D Arrays

Converting 2D arrays into an array of left and right analog samples

The final step in converting I²S data to left and right analog data is converting the 2D arrays into two 1D arrays of left and right data.  I2S_ConvertToAnalogData.vi does this by reading the MSB and placing it in the MSB of an I32.  The next column of the 2D array is written to the MSB-1.  This continues until all the columns of data are read.  The result is a 1D array of left channel analog samples and a 1D array of right channel analog samples.  In order to achieve proper scaling and formatting, the bits are shifted right 32-<bit encoding>.  

Physical Implementation

To keep the I²S example hardware independent, the I²S data is encoded, passed via software, and then decoded.  Although this shows how to encode/decode I²S data, most applications will be using a digital device to generate or acquire I²S data.  The recommended board for I²S generation/acquisition depends on your specific needs.  In general, National Instruments High Speed Digital I/O (HSDIO) cards are recommended due to their digital feature set.  For functional test, the 6535/6/7 boards should provide the required features at a lower cost.  If you are performing characterization, consider the 6541/2 and 6551/2 boards which add additional timing and voltage configuration.

Below are the three implementations of the I²S bus according to the I²S specifications along with suggested shipping examples to give users a starting point when attempting to generate/acquire I²S data.

Transmitter is Master

NI Board is Transmitter

In this setup, the transmitter is generating the Clock, Word Select, and Serial data.  I2S_Encode.vi can build the needed signals and the HSDIO card can generate these patterns.  If this best describes your setup, consider the Dynamic Generation.vi (654x, 655x) and Cont Write Dig Port-Ext Clk.vi (653x) shipping examples.

NI Board is Receiver

In this setup, the receiver is acquiring the Clock, Word Select, and Serial data.  If there is only one DUT, or the data lines are phase locked, consider using the Serial Clock as the HSDIO card's sample clock.  This will simplify the system as a single clock can correctly acquire all the data.  If there are multiple unsynchronized DUTs, the data will need to be over-sampled and then this over-sampling removed using the I2S_RemoveDataOversampling.vi.

Once the data is acquired, use I2S_Decode.vi to process the data.  A good starting place for hardware example code are the Dynamic Acquisition with Fetch.vi (654x,655x) or Cont Read Dig Port-Ext Clk.vi (653x) shipping examples.

Receiver is Master

NI Board is Transmitter

In this setup, the receiver is generating the Serial Clock and Word Select signals.  Based on these signals, the transmitter generates the I²S data.  The NI HSDIO cards can generate data based on the provided Serial Clock however, in order to synchronize the communication between the two devices, the Word Select line should be used as a start trigger.  It is important to note that there is no synchronization after the start trigger.  If this is a system requirement, consider the NI R Series or FlexRIO product lines, as these products can be programmed to have this behavior.

NI Board is Receiver

The receiver needs to generate the Serial Clock and Word Select lines while acquiring the serial data.  One important consideration in this setup is insuring a consistent timing relationship between the start of the acquisition and generation.  For a good starting point, consider the Dynamic Generation and Acquisition-Demo.vi (654x, 655x).

Controller is Master

NI Board is Transmitter

Although the Serial Clock and Word Select lines originate from the controller instead of the receiver, the behavior of the transmitter is the same as when the Receiver is Master.  For more information, please see the NI Board is Transmitter section of the Receiver is Master case.

NI Board is Receiver

Since all the signals arrive at the receiver, this is very similar to NI Board is Receiver when the Transmitter is Master case.  For programming recommendations, see the NI Board is Receiver section of the Transmitter is Master case.

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