LabVIEW 2009 FPGA Module Known Issues
PrintOverview
This document contains the LabVIEW 2009 FPGA Module known issues
that were discovered before and since the release of
LabVIEW 2009. Not every issue known to NI will appear on this
list; it is intended to only show the severe and more common issues
that can be encountered.
The LabVIEW 2009 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.
Windows 7
National Instruments is committed to maintaining compatibility with Microsoft Windows technology changes. However, NI has become aware of a number of issues of potential significance regarding Microsoft Windows 7. To learn how Windows 7 affects your use of NI products, visit ni.com/info and enter the Info Code windows7.
Fields
Each known issue includes these fields:- Issue ID
- Legacy ID - The issue's legacy ID from NI's deprecated bug reporting database (if applicable)
- Issue Title
- Problem Description
- Workaround
- Reported Version - the earliest version of LabVIEW the issue was reported in
- Resolved Version - version the issue was resolved or was no longer applicable
- Date Added - the date the issue was added to the document
(not reported date)
Document Organization
The following document displays the issues by issue category.Known Issues by Category
Contacting NI
You can contact us by phone, email, or the discussion forums. Visit the NI Website to contact us.
Known Issues by Category
The following items are known issues in LabVIEW 2009 FPGA Module Known Issues sorted by Category.
| ID | Known Issue | |||||
|---|---|---|---|---|---|---|
| Functions, VIs, and Express VIs | ||||||
| 172032 Return |
FPGA FIFO reset behavior When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. Workaround: To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Download from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
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| 172016 Return |
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.
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| 172008 Return |
Incorrect mutation You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 2009, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node. Workaround: You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs.
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| 171971 Return |
TCP must be installed Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Workaround: TCP must be installed.
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| 169366 Return |
Compile Server is done compiling but still uses 100 percent of CPU The Compile Server display shows that it has completed compilation, but according to the task manager it is using 100 percent of the CPU. The LabVIEW Client dialog may appear unresponsive because it is in the middle of a network transaction with the compile server. Further attempts to communicate with the compile server while it is in this state may lead to confusing error messages from the client dialog. Workaround: Restart the Compile Server by clicking the Stop Server button. This action will cause the client dialog to become responsive and it will display an error dialog about communicating with the server. After the Compile Server is restarted, click Reconnect to Compilation on the FPGA VI to retrieve the results of the compilation.
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| 162027 Return |
Control VIs from 8.5.x and earlier do not automatically migrate to the FPGA Module 2009 implementation of the Control VIs Control VIs from 8.5.x and earlier will work with LabVIEW 2009. However, if you replace these legacy VIs with the current version of these VIs, you might need to adjust terminal names, single-cycle Timed Loop support, and fixed-point support. Workaround: N/A
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| 151047 Return |
Fixed-Point Math Library node fails to compile if pipeline stage exceeds 64 If the number of pipeline stages exceeds 64, compile will report the following error Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more. This usually happens in configurations of fixed-point math library node to have output data width of 64 and throughput of 1 cycle/sample inside SCTL. Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 stages of pipeline is needed, go to the LabVIEW folder and find the file ...\resource\RVI\StockIO\private\topModGenUtilities\vhdl_area.opt. Open the file with a text editor, before the line "run", add a line "set -loop_iteration_limit 128"; Save the file and recompile the VI.
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| 107560 Return |
Interrupt VIs saved to previous versions of LabVIEW are broken If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable. Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.
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| 101193 Return |
Read/Write Control function allows you to select disabled control If you disable a control, you can still select the control from the Read/Write Control function, which returns error -61059. Workaround: Do not select the control from the Read/Write Control function.
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| 98807 Return |
Host VI does not get notified of changes when building an application If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application. Workaround: You must open and save the host VI before building an application.
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| 95971 Return |
Error compiling empty external clock loop If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error. Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.
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| 93395 Return |
Modifying conditional disable symbols requires recompile If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures. Workaround: Recompile the FPGA VI.
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| 51871 Return |
Multiplying fixed-point data might not meet 40 MHz timing If you use the Multiply function with inputs above 32 bits that contain fixed-point data, the function might not meet 40 MHz timing requirements. Workaround: You can place the Multiply function inside a single-cycle Timed Loop that is configured at a lower clock rate.
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| 43704 Return |
Error checking on Read/Write Control function The FPGA Module checks the Read/Write Control function to see if the timeout bit is set after all of the reads/writes have completed. However, race conditions for when the error message gets reported might exist. As a result, the FPGA Module might return the error on a Read/Write Control function other than the Read/Write Control function where the error occurred. Workaround: N/A
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| 42189 Return |
Cannot build installer if host VI references FPGA VI If the Open FPGA VI Reference function refers to an FPGA VI, you might not be able to build an installer. Workaround: You can configure the Open FPGA VI Reference function to refer to a bitfile to create an installer.
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Document last updated on 8/4/2009
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