LabVIEW FPGA Module Training
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Welcome to the LabVIEW FPGA Module Training Course. This free training material is divided into 8 lessons. Below you will see the outline for each section followed by a PowerPoint file with slides and notes. Some lessons include a Word document with exercise instructions and a zip file containing LabVIEW files with exercise solutions. This material was developed to be an introduction to LabVIEW FPGA. Previous knowledge of LabVIEW is highly recommended.
Table of Contents
- Lesson 1 - Introduction to FPGA
- Lesson 2 - LabVIEW FPGA Basics
- Lesson 3 - General FPGA Programming Techniques
- Lesson 4 - FPGA I/O
- Lesson 5 - FPGA Timing and Loop Execution
- Lesson 6 - Data Transfer Between FPGA and Host
- Lesson 7 - Synchronizing FPGA and Host Data Transfers
- Lesson 8 - Optimizing FPGA Applications for Speed and Size
Lesson 1 - Introduction to FPGA
- Introduction to FPGA technology
- LabVIEW FPGA system components
- Applications
Lesson 2 - LabVIEW FPGA Basics
- Hardware configuration
- Development process for LabVIEW FPGA applications
- Reconfigurable I/O architectures
Lesson 3 - General FPGA Programming Techniques
3 FPGA Programming Technique.pptx
- Exploring the LabVIEW FPGA Palette
- Basic FPGA VI
- Parallelism and Shared Resources
- Interger Math
Lesson 4 - FPGA I/O
- Configuring FPGA I/O
- Exploring the LabVIEW FPGA I/O Palettes
- I/O Types
Lesson 5 - FPGA Timing and Loop Execution
5 FPGA Timing and Execution.pptx
- Timing Functions
- Loop Execution Using Different Timing Functions
- Parallel Loop Execution
- Loop Synchronization
- Data Sharing
Lesson 6 - Data Transfer Between FPGA and Host
- FPGA Interface Palette
- Open FPGA VI Reference
- Read/Write Control
- Close VI Reference
- Invoke Node
- DMA
Lesson 7 - Synchronizing FPGA and Host Data Transfers
7 Advanced Host Integration.pptx
- Interrupt-based Handshaking
- DMA-based Handshaking
Lesson 8 - Optimizing FPGA Applications for Speed and Size
8 FPGA Optimization for Size and Speed.pptx
- Benchmarking
- How LabVIEW is transformed for FPGA
- Optimizing for Speed
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This tutorial (this "tutorial") was developed by National Instruments ("NI"). Although technical support of this tutorial may be made available by National Instruments, the content in this tutorial may not be completely tested and verified, and NI does not guarantee its quality in any way or that NI will continue to support this content with each new revision of related products and drivers. THIS TUTORIAL IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND AND SUBJECT TO CERTAIN RESTRICTIONS AS MORE SPECIFICALLY SET FORTH IN NI.COM'S TERMS OF USE (http://ni.com/legal/termsofuse/unitedstates/us/).