LabVIEW FPGA Semaphore IP
When developing applications using LabVIEW FPGA it becomes necessary to use shared resources such as a local and global variables, non-reentrant VIs, etc. in multiple locations on the diagram.
Software: LabVIEW Full Development System
Hardware: CompactRIO, Reconfigurable I/O

A Design Pattern for CompactRIO Fail-Safe Control
This example provides a framework for control systems which must behave predictably in the event of a hardware or software failure. The example demonstrates FPGA safe states and FPGA monitored watchdogs for the Real-Time controller.
Software: LabVIEW Professional Development System
Hardware: CompactRIO, Reconfigurable I/O

A Design Pattern for Adding Licensing to a LabVIEW Real-Time Application
Adding licensing to a LabVIEW Real-Time application can protect a deployed application from being copied and run on another similar or identical set of hardware without obtaining a license from the vendor or distributor of the application.
Software: LabVIEW Full Development System
Hardware: Compact FieldPoint, CompactRIO, PXI/CompactPCI

Reference Example: SoftMotion 2.1 Servo PID Tuning
Note: This example is has generic structures and code that make it an applicable utility for general servo PID tuning on LabVIEW FPGA targets. The PID FPGA VI implemented in this example is available with SoftMotion Development Module 2.
Software: LabVIEW Full Development System

A Design Pattern for Emulating an LVDT with the NI PXI-78xxR
Download the example code for emulating a Linear Variable Differential Transformer (LVDT) sensor for HIL and other test applications using LabVIEW FPGA and the NI 78xxR RIO boards.
Software: LabVIEW Professional Development System

Reference Example: Streaming Data from FPGA to cRIO to Windows Example
This is an optimized example for streaming data from FPGA to cRIO to Windows. Note: This example is optimized for throughput and CPU Usage. Therefore, some determinism is lost. The cases where this is true is documented below.
Software: LabVIEW Professional Development System
Hardware: CompactRIO

Multiply Accumulate (MAC) optimized for DSP48E slice using HDL node
A Multiply Accumulate (MAC) operation is a common type of operation in FPGA that can be carried out in normal logic or optimized with the Virtex-5 FPGAs using a special slice called the DSP48E.
Software: LabVIEW Professional Development System
Hardware: Reconfigurable I/O

Example VI for C Series I/O Modules in Any Deployment
This example VI demonstrates how to read data from a C Series I/O Module that has been deployed to any platform - the USB Single Module Carrier, CompactDAQ, and even the embedded CompactRIO - with a single LabVIEW application.
Software: LabVIEW Professional Development System
Hardware: CompactDAQ, CompactRIO, Portable DAQ, Real-Time, Reconfigurable I/O

Using the NI cRIO-9151 With High Channel Count Applications
This example shows how to use the NI-781xR RIO boards along with multiple NI cRIO-9151 and C-Series modules to perform simultaneous, high channel-count acquisition. The follow example uses the following hardware to acquire 60 channels at 50 kS/s/channel: NI-7813R
Hardware: CompactRIO, Reconfigurable I/O

Reference Example: Oversampled Frequency Measurements with Multiple Counters on FPGA
This application is an example using cRIO and FPGA to do multi-channel oversampled frequency measurements which are measured over a set time period as a means to increase measurement accuracy.
Software: LabVIEW Professional Development System
Hardware: CompactRIO