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Using PID on FPGA Targets (PID and Fuzzy Logic Toolkit)

LabVIEW 2012 PID and Fuzzy Logic Toolkit Help

Edition Date: June 2012

Part Number: 370401J-01

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You can use the PID (FPGA) Express VI to implement single-channel or multi-channel PID on a LabVIEW FPGA target. The PID (FPGA) Express VI implements a fixed-point PID algorithm. Refer to the VI topic for details about the algorithm the VI uses.

Note  The PID (FPGA) Express VI is available only if you install both the PID and Fuzzy Logic Toolkit and the LabVIEW FPGA Module.

Implementing a Single-Channel PID on FPGA Targets

To configure the PID (FPGA) Express VI for a single-channel implementation, enter 1 in the Number of channels control on the configuration dialog box. For single-channel PID implementations, any changes you make to the PID parameters on the host VI take effect immediately on the FPGA target.

(NI-RIO) If you have the NI-RIO software installed, refer to the Using Discrete PID - cRIO project in the labview\examples\CompactRIO\FPGA Fundamentals\Analysis and Control\PID Toolkit directory for an example of a single-channel PID implementation on an FPGA target.

(NI-RIO) If you have the NI-RIO software installed, you also can refer to the Using Discrete PID - R Series project in the labview\examples\CompactRIO\FPGA Fundamentals\Analysis and Control\PID Toolkit directory.

Implementing a Multi-Channel PID on FPGA Targets

To configure the PID (FPGA) Express VI for a multi-channel implementation, enter a number greater than 1 in the Number of channels control on the configuration dialog box. To handle the values for each channel, the host VI can include an initialization loop and processing loop, which you can use to modify parameters or reset channels.

Initialization Loop on the Host VI

The initial parameter values you enter on the configuration dialog box for the PID (FPGA) Express VI set the initial values for all channels. To specify unique values for individual channels, you must create an initialization loop on the host VI.

In the initialization loop, you might update the parameter values of some channels while other channels retain the initial values you specified in the configuration dialog box. In the following block diagram, the initialization loop initializes the parameters of all channels.

Note  The following block diagram contains some functions available only if you install FPGA target driver software or the LabVIEW FPGA Module.

Processing Loop on the Host VI

After initializing the PID parameters and while running the VI on the FPGA target, you might want to modify parameters or reset channels on a per-channel basis, without affecting the execution of other channels. Create a processing loop on the host VI to modify parameters or reset channels asynchronously during execution of the FPGA VI.

Resetting a PID channel resets the internal channel states to 0 and restarts the PID algorithm while using either the parameter values stored in memory or the parameter values from the host VI. To modify different parameters, you must specify the channel index, which tells the PID algorithm the channel number to which to apply the new parameter values. The following block diagram shows an example of a processing loop.

Note  The following block diagram contains some functions available only if you install FPGA target driver software or the LabVIEW FPGA Module.


 

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