Per Cycle Tristate

NI Digital Waveform Generator/Analyzer Help

Edition Date: June 2013

Part Number: 370520P-01

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NI digital waveform generator/analyzers allow you to drive a logic 0 or a 1 during every active period of the Sample clock. Some NI devices have the additional capability of driving a logic 0, logic 1 or tristating the channel during every active clock cycle. This capability is referred to as per cycle tristate. This functionality allows you to create waveforms composed of 0, 1, and Z values on any channel and on any sample. For each sample in the waveform, you can select which channel to tristate by inserting Z values in the waveform at that location. When using per cycle tristate, some devices support less channels than when in binary mode. Refer to the Per Cycle Tristate topic for your specific device for more information on channels available for per cycle tristate.

Per cycle tristate is useful for communicating or testing bidirectional digital channels. For example, communicating with a memory device may require the generator to drive address and data channels during a write, but tristate the data channels during a read.

Notes  Per cycle tristate is currently supported only on NI 6547/6548/655x devices.
When switching a channel from driving to receiving data at high-speeds, allow enough time for all the samples to propogate through the system so that signal reflections resulting from tristating the channel do not affect the signal transmission.
Before writing any waveforms using per cycle tristate, you must first configure the device to support extended data states by setting the Supported Data States property to O, 1, Z (tristate) or the NIHSDIO_ATTR_SUPPORTED_DATA_STATES attribute to NIHSDIO_VAL_STATES_0_1_Z.

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