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Patterns acquired by the NI 6555/6556 are received using a dual-comparator architecture. One comparator is assigned to each acquisition threshold (Acquisition Voltage High and Acquisition Voltage Low). Refer to the NI PXIe-6555/6556 Specifications for more information about input voltage thresholds for each logic family setting and for accuracy and range requirements.
The output of the dual comparators are combined into a single bit using the selected data interpretation method. The data is sampled by the Pattern Acquisition Timing and Control module before being sent to the Pattern Acquisition Engine for storage into Acquisition Memory.
You can programmatically set the Termination Mode property or the NIHSDIO_ATTR_DATA_TERMINATION_MODE attribute to high impedance or 50 Ω, referenced to a configurable voltage, VTT. When configured for 50 Ω impedance, the variable voltage driver is enabled and drives VTT.
The following image shows the comparator circuitry on the NI 6555/6556.