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A common NI 6551/6552 configuration is to connect the output terminals of your NI device directly to your device under test (DUT). Most digital logic inputs have an input impedance of 1–10 KΩ. Since your NI 6551/6552 is designed to be used in a 50 Ω environment, connecting the NI device output terminals directly to the input of your DUT effectively creates an unterminated load configuration.
While this unterminated configuration does not provide the absolute highest level of signal quality, there are many advantages to an unterminated configuration. First, very good signal levels are possible if you ensure that you have the cleanest possible 50 Ω characteristic impedance transmission line. Second, this unterminated configuration allows you to directly wire to your DUT without the need for additional termination resistors. Lastly, given that at DC there is effectively a voltage divider between the 50 Ω Zs resistance and the high-impedance Zt of your DUT, having an unterminated load preserves the largest possible voltage swings at the DUT according to the following formula: Vt = Vs×(Zt/(Zs + Zt))
Therefore, for a DUT with an input impedance of 1 kΩ, programming a generation voltage level of 3.3 V at the NI 655x source produces a 3.3 V × (1000/1050) = 3.14 V swing.
The unterminated load generates reflections in the transmission line. The load reflections, however, are absorbed at the source and not re-reflected back to the load, thus preserving the signal integrity. Practically, the source impedance does not perfectly match the transmission line impedance; therefore, a small fraction of the reflected wave is re-reflected back toward the load. This second reflection creates small signal aberrations and a low level of inter-symbol interference.
For example, a 5% mismatch at the source results in a 2.5% re-reflection back at the load:
Γs = (1.05 - 1)/(1.05 + 1) ≈ 2.5%
The unterminated load configuration is easy to use with a terminated source, such as the NI 6551/6552, and is recommended for all applications except the most demanding in regard to timing precision or signal integrity. For applications demanding the highest levels of signal quality and timing precision, NI recommends that you seriously consider following the recommendations of the terminated load configuration.
For applications requiring the highest levels of signal integrity and timing accuracy, NI strongly recommends carefully controlling the termination impedance at the end of the transmission line. To control the termination impedance, add a parallel termination resistor to ground as close as possible to the digital input pin of the device under test (DUT). In this configuration, the transmission line is terminated at both ends of the transmission line, which produces the highest possible signal integrity.
Ideally, the source impedance, ZS, and the characteristic impedance of the transmission line, Z0, should be kept as close as possible to 50 Ω as this gives you the best possible signal quality.
However, depending on your NI device, having all the lines terminated into 50 Ω may violate the maximum current specifications for your NI device. Refer to the specifications document for your device for more information about the maximum current for your device to determine how many lines you can simultaneously terminate into 50 Ω.
While a Zt of 50 Ω is ideal, you can also use values as high as 150 Ω without significantly affecting signal quality. Using this higher resistance value enables you to increase the voltage swing across the DUT and decrease the drive current requirements on your NI 6551/6552.
Given that at DC there is effectively a voltage divider between the 50 Ω ZS resistance and the termination resistance, having a terminated load reduces the largest possible voltage swings at the DUT according to the following formula: Vt = Vs×(Zt/(Zs + Zt))
Therefore, for a 50 Ω termination, programming a generation voltage level of 3.3 V at the NI 6551/6552 source produces a 3.3 V x (50/100) = 1.65 V swing. This reduced voltage swing at the DUT should be considered when you create your system.