Synchronizing Multiple Devices

NI Digital Waveform Generator/Analyzer Help

Edition Date: June 2013

Part Number: 370520P-01

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Synchronizing multiple devices can occur to varying degrees. On the simplest level, the devices may be essentially operating independently with triggers and events passed between them to regulate operations. However, in more tightly integrated systems, the Sample clocks are phase aligned between all the devices, and all devices are triggered at the same time. For the NI digital waveform generator/analyzers, this alignment is done using the Sample clock source, Reference clock source, and by using NI-TClk for clock alignment and trigger routing.

Sample Clock Phase Alignment

  • PXI Devices

For PXI digital waveform generator/analyzers using an internal clock source, the internal clock source can be phase aligned to the PXI_CLK10 signal on the backplane by selecting PXI_CLK10 as the Reference clock source. NI-TClk ensures that the Sample clock dividers on each PXI device are in phase for Sample clock alignment.

For PXI digital waveform generator/analyzers using an external clock source (CLK IN, STROBE, or PXI_STAR), ensure that the Sample clocks are aligned when presented to the devices. If you are using PXI_STAR as the external clock source, the matched length traces on the PXI backplane assist in keeping the distributed Sample clocks aligned. You can use a device like the NI PXI-5404 or NI PXI-6653 to distribute clocks on PXI_STAR.

  • PXIe Devices

For PXIe digital waveform generator/analyzers using an internal clock source, the internal clock source can be phase aligned to the PXIe_CLK100 signal on the backplane by selecting PXIe_CLK100 as the Reference clock source. NI-TClk ensures that the Sample clock dividers on each PXIe device are in phase for Sample clock alignment.

For PXIe digital waveform generator/analyzers using an external clock source (CLK IN or STROBE), ensure that the Sample clocks are aligned when presented to the devices.

  • PCI Devices

For PCI digital waveform generator/analyzers using an internal clock source, the internal clock source can be phase aligned to a 10 MHz reference signal on the RTSI 7 line of the RTSI connector. Configure the PCI device at one end of the RTSI cable to drive the Onboard Reference Clock onto RTSI 7, and configure all of the PCI devices to receive their Reference clock from RTSI 7. NI-TClk ensures that the Sample clock dividers on each device are in phase for Sample clock alignment.

For PCI digital waveform generator/analyzers using an external clock source (CLK IN or STROBE), ensure that the Sample clocks are aligned when presented to the devices.

Trigger Routing

The NI-TClk software uses the PXI trigger bus/RTSI bus lines to deterministically pass triggers between multiple NI digital waveform generator/analyzers. Refer to the multidevice NI-TClk examples for more information. Deterministic trigger routing ensures that all NI digital waveform generator/analyzers in the system start on the same sample.

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