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Short Name: DataPos.Delay
Property of niHSDIO
Specifies the delay after the Sample clock rising edge when the device generates or acquires a new data sample. Data delay is expressed as a fraction of the clock period (for example, a fraction of 1/Sample clock rate). This property is relevant only when the Data Position property is set to Delay From Sample Clock Rising Edge . This property is valid only when the position parameter of the niHSDIO Configure Data Position VI is set to Delay From Sample Clock Rising Edge for these channels.
|Note On NI 6555/6556 devices, valid values range from –1 to 2 clock cycles in increments of 0.001 cycles. Delay on NI 6555/6556 devices is configured on a per channel basis.|
|Note To configure a delay on NI 656 x devices, you must delay all channels in the session. NI-HSDIO returns an error if you apply a delay to only a partial channel list.|
The NI 6547/6548 devices support multibank data delay. All channels configured to Delay From Sample Clock Rising Edge and assigned to the same data delay bank must share a data delay value, even if channels on that bank are configured to Sample clock rising edge or Sample clock falling edge . NI-HSDIO returns an error if you set different delay values for two channels within the same bank. Refer to the multibank data delay topic for your device to determine which channels belong to which bank.
The following table lists the characteristics of this property.
|High-level VIs||niHSDIO Configure Data Position Delay|