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Short Name: DataPos.Position
Property of niHSDIO
Specifies which edge of the Sample clock signal is used to time the generation or acquisition. You can also configure the device to generate or acquire data at a configurable delay past each rising edge of the Sample clock.
|Note To configure a delay on NI 656 x devices, you must delay all channels in the session. NI-HSDIO returns an error if you apply a delay to only a partial channel list.|
Refer to the Data Position Delay property for more information about multibank data delay.
|Sample clock rising edge (18)||
The device samples or generates data on the Sample clock rising edge.
|Sample clock falling edge (19)||
The device samples or generates data on the Sample clock falling edge.
|Delay from sample clock rising edge (20)||
The device samples or generates data with a delay from the Sample clock rising edge. Specify the delay using the Data Position Delay property. This choice has more jitter than the rising or falling edge values. Certain devices have Sample clock frequency limitations on when a custom delay can be used. Refer to the device documentation for details.
The following table lists the characteristics of this property.
|High-level VIs||niHSDIO Configure Data Position|