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Short Name: DataPos.TrigDelay
Property of niHSDIO
Specifies, per channel, the delay after the Sample clock rising edge when the device samples on a trigger. Trigger delay is expressed as a fraction of the clock period (for example, a fraction of 1/Sample clock rate).
|Note This property is supported only on PFI 1 and PFI 2 on NI 6555/6556 devices.|
Valid values range from –1 to 2 clock cycles in increments of 0.001 cycles.
The default value is 0.
The following table lists the characteristics of this property.