I/O Resources

NI High-Speed Digitizers Help (NI-SCOPE 16.1)

Edition Date: January 2017

Part Number: 370592AB-01

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NI-SCOPE 18.7 (English | Japanese)
Note Note  This functionality is only available when using instrument design libraries.

Use FPGA I/O nodes to connect to the device I/O. You can configure FPGA I/O nodes for reading or writing. The FPGA I/O nodes connect to the front panel I/O, backplane I/O, and internal status signals of the module. The following tables describe LabVIEW FPGA I/O resources visible in the LabVIEW project.

Note Note  Each resource must be used inside of its Required Clock Domain. For more information about clock domains in LabVIEW FPGA Module, refer to the Implementing Multiple Clock Domains topic in the LabVIEW FPGA Module Help.

Sample Data In

Name Description Data Type Access Method Required Clock Domain
Channel N Contains raw data from the channel N ADC, where N is a channel number from 0 to the maximum channel number of your device. The data is presented as 2 samples per cycle at 125 MHz loop rate. Array of two fixed-point numbers1 <±, 14, 1>2 Read I/O Node Data Clock
Channel Data Valid For each channel, this array contains TRUE if the channel's sample is valid and FALSE if the channel's sample is not valid. Array of four or eight Boolean values, depending on device channel count Read I/O Node Data Clock
Channel Overload For each channel, this array contains TRUE if an overvoltage condition occurred on the channel and FALSE if no overvoltage condition occurred on the channel. Array of four or eight Boolean values, depending on device channel count Read I/O Node Any
1 The sample at index 0 corresponds to the first sample read from the ADC, while the sample at index 1 corresponds to the second sample read from the ADC.
2 The <±, 14, 1> notation corresponds to a signed, fixed-point number with a 14-bit word length and a 1-bit integer word length.

Time-to-Digital Converter (TDC)

Name Description Data Type Access Method Required Clock Domain
TDC Enable Setting this value to TRUE enables the Time-to-Digital Conversion circuit (TDC). Setting this value to FALSE disables the TDC. Boolean Write I/O Node Any
TDC Assert Setting this value to TRUE asserts a digital signal (a "TDC pulse") synchronously the Data Clock signal. Boolean Write I/O Node Data Clock
TDC Deassert Setting this value to TRUE asserts a digital signal (a "TDC pulse") synchronously to the PXIe_Clk100 signal. Boolean Write I/O Node PXIe_Clk100
TDC Expanded Pulse Signal from the TDC that is an expanded pulse (500x) generated from the use of TDC Assert and TDC Deassert. The pulsewidth of this signal is proportional to the delay between edges of Data Clock and PXIe_Clk100. Boolean Read I/O Node Any

Trigger and Digital

Name Description Data Type Access Method Required Clock Domain
PFI N Controls PFI line N, where N is a PFI line number from 0 to 7. This signal is connected with the AUX I/O front panel connector of the module. To access this digital I/O line, use an FPGA I/O node configured for reading or writing, or use the Set Output Enable and Set Output Data methods. Boolean Read I/O Node, Write I/O Node, I/O Method Any

PXI

Name Description Data Type Access Method Required Clock Domain
PXI_TrigN Controls PXI trigger line N, where N is a PXI trigger line number from 0 to 7. To access this digital I/O line, use an FPGA I/O node configured for reading or writing along with the Set Output Enable and Set Output Data methods. For proper device and PXI system functionality when using PXI triggers with the LabVIEW FPGA Module, follow the guidelines in PXI Triggers. Boolean Read I/O Node, Write I/O Node, I/O Method Any
PXIe_Sync100 This signal becomes TRUE one PXIe_CLK100 cycle before each rising edge of PXI_CLK10. It can be sampled and used as an enable signal to mirror the behavior of PXI_CLK10. Boolean Read I/O Node PXIe_Clk100
PXIe_DStarB Trace length matched signal driven from the System Timing Module slot to the NI 5170R/5171R. Boolean Read I/O Node Any
PXIe_DStarC Trace length match signal driven from the NI 5170R/5171R to the System timing module. Boolean Write I/O Node Any

Device Status

You can monitor device status, power, and temperature using instrument design libraries. For more information on device monitoring, refer to the overview of the Configuration instrument design library.

Name Description Data Type Access Method Required Clock Domain
Module Temperature This resource provides the FPGA temperature reading from the on-chip temperature sensor. To calculate the value in degrees Celsius, use the following transfer function:
Temperature (°C) = [(Temperature Measurement * 503.975) / 4096] - 273.15
16-bit signed integer Read I/O Node 40 MHz Onboard Clock
Module Power Consumption This resource provides the current device power consumption reading. This instantaneous power reading is the sum of the power consumption reports of the 3.3 V sensor and the 12 V sensor. The reading is in centiWatts (cW). To calculate the value in Watts, use the following transfer function:
Power Consumption (W) = Power Measurement / 100
16-bit signed integer Read I/O Node 40 MHz Onboard Clock
Temperature Error Returns TRUE when the module has exceeded its safe operating temperature range. If this condition occurs, shut down the chassis and check for proper cooling. Boolean Read I/O Node Any
AUX I/0 Power Enable Setting this value to TRUE enables the 3.3 V power source from the AUX I/O front panel connector. Boolean Write I/O Node Any
AUX I/O Power Fault Returns TRUE if an overcurrent condition has occurred at the 3.3 V power source from the AUX I/O front panel connector. For more information, refer to External Power. Boolean Read I/O Node Any

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