You are here: NI Home > Support > Product Reference > Manuals > LabVIEW 8.6 Real-Time Module Help

Owning Palette: SMP CPU Utilities VIs

Installed With: RT Module

Assigns CPUs to pools for automatic load balancing. This VI assigns CPUs to one of four possible states: System pool only, Timed Structures pool only, both pools, or no pool (reserved). This VI outputs the bit masks that specify the CPUs assigned to each pool.

Details  

	CPU pools specifies the pool assignments of each CPU in the system. This input is an array of enums. The enum contains the four possible states of a CPU and each element of the array represents a CPU. The array indices 0 - N correspond directly to the CPU indices 0 - N. Reserved Assigns the CPU to neither pool. The CPU is reserved for Timed Structures configured for manual processor assignment. System & Timed Structures Assigns the CPU to both the System pool and the Timed Structures pool for automatic load balancing of all threads that are not manually assigned to a particular CPU. System Assigns the CPU to the System pool for automatic load balancing of non-timed-structure threads. Timed Structures Assigns the CPU to the Timed Structures pool for automatic load balancing of timed structure threads.
	error in describes error conditions that occur before this VI or function runs. The default is no error. If an error occurred before this VI or function runs, the VI or function passes the error in value to error out. This VI or function runs normally only if no error occurred before this VI or function runs. If an error occurs while this VI or function runs, it runs normally and sets its own error status in error out. Use the Simple Error Handler or General Error Handler VIs to display the description of the error code. Use exception control to treat what is normally an error as no error or to treat a warning as an error. Use error in and error out to check errors and to specify execution order by wiring error out from one node to error in of the next node. status is TRUE (X) if an error occurred before this VI or function ran or FALSE (checkmark) to indicate a warning or that no error occurred before this VI or function ran. The default is FALSE. code is the error or warning code. The default is 0. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source specifies the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning. The default is an empty string.
	assigned CPU pools returns the CPU pool assignments. Reserved The CPU is not assigned to a pool. The CPU is reserved for Timed Structures configured for manual processor assignment. System & Timed Structures The CPU is assigned to both the System pool and the Timed Structures pool for automatic load balancing of all threads that are not manually assigned to a particular CPU. System The CPU is assigned to the System pool for automatic load balancing of non-timed-structure threads. Timed Structures The CPU is assigned to the Timed Structures pool for automatic load balancing of timed structure threads.
	system mask returns a bit mask corresponding to System pool assignments.
	timed structures mask returns a bit mask corresponding to the Timed Structures pool assignments.
	error out contains error information. If error in indicates that an error occurred before this VI or function ran, error out contains the same error information. Otherwise, it describes the error status that this VI or function produces. Right-click the error out front panel indicator and select Explain Error from the shortcut menu for more information about the error. status is TRUE (X) if an error occurred or FALSE (checkmark) to indicate a warning or that no error occurred. code is the error or warning code. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source describes the origin of the error or warning and is, in most cases, the name of the VI or function that produced the error or warning.

RT Set CPU Pool Assignments Details

On an N-CPU system, the bits of the bit mask correspond to CPUs 0 through N-1. The right-most bit of each bit mask corresponds to CPU 0 and the left-most bit corresponds to CPU 31, if such a CPU exists in the system.

Refer to the Specifying the Set of CPUs Available for Automatic Load Balancing topic for more information about CPU pools.