|NI-RFSG 18.1 Help|
|NI-RFSG 18.2.1 Help|
|NI-RFSG 19.1 Help|
Short Name: PXI Chassis Clk 10 Source
Property of niRFSG
Specifies the clock source for driving the PXI 10 MHz backplane Reference Clock. This property is configurable if the PXI-5610 upconverter module is installed in only Slot 2 of a PXI chassis. To set this property, the NI-RFSG device must be in the Configuration state.
Supported Devices: PXI-5610, PXI-5670/5671
Only certain combinations of this property and the Reference Clock Source property are valid, as shown in the following table.
|PXI Chassis Clk 10 Source Property Setting||Valid Reference Clock Source Property Setting|
|None, OnBoard Clock||OnBoard Clock|
|None (PXI 10 MHz oscillator), RefIn (Reference signal connected to the REF_IN connector of the upconverter; backplane locked to REF_IN; upconverter locked to backplane)||PXI_CLK|
System Reference Clock
|Do not drive signal ()||
Do not drive the PXI_CLK signal.
Uses the highly stable oven-controlled onboard Reference Clock to drive the PXI_CLK signal.
Uses the clock present at the front panel REF IN connector to drive the PXI_CLK signal.
The following table lists the characteristics of this property.
|High-level VIs||niRFSG Configure PXI Chassis Clk10|