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Executes one or more subdiagrams, or frames, sequentially each iteration of the loop at the period you specify. Use the Timed Loop when you want to develop VIs with multirate timing capabilities, precise timing, feedback on loop execution, timing characteristics that change dynamically, or several levels of execution priority. Right-click the structure border to add, delete, insert, and merge frames. If you use the Timed Loop in an FPGA VI, the loop executes one subdiagram at the same period as an FPGA clock.

Double-click the Input Node or right-click the structure and select Configure Timed Loop to display the Configure Timed Loop dialog box, where you can configure the Timed Loop. The values you enter in the Configure Timed Loop dialog box appear next to the input terminals on the Input Node.

Unlike the While Loop, the Timed Loop does not require wiring to the stop terminal. If you do not wire anything to the stop terminal, the loop will run interminably.

Refer to the Configuring Timed Loops topic for more information about using and configuring the Timed Loop. Refer also to the Nodes of the Timed Loop topic and the Nodes of the Timed Loop with Frames topic for more information about nodes of the Timed Loop.

Examples

Refer to the following VIs for examples of using the Timed Loop:

• Offset for the Timed Loop VI: labview\examples\general\timedloop.llb
• Optimizing timed loop rate VI: labview\examples\general\timedloop.llb
• PAC Simulation With Frames VI: labview\examples\general\plat-timedloopframes.llb
• PAC Simulation VI: labview\examples\general\timedloop.llb
• Resettable Timing VI: labview\examples\general\timedloop.llb