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Configure Condition Dialog Box

LabVIEW 2013 Help

Edition Date: June 2013

Part Number: 371361K-01

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Requires: Base Development System

Right-click a Conditional Disable structure and select Add Subdiagram After, Add Subdiagram Before, Duplicate Subdiagram, or Edit Condition For This Subdiagram from the shortcut menu to display this dialog box.

Use this dialog box to configure when a subdiagram executes.

This dialog box includes the following components:

  • Expression—Specifies a set of conditional statements that LabVIEW evaluates to determine the active subdiagram of the structure. The expression includes the following components:
    • Symbol(s)—Lists all available symbols.

      SymbolDescription
      CPUSpecifies the processor on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
      FPGA_EXECUTION_MODESpecifies to execute different code within an FPGA VI depending on whether the VI executes on the FPGA target, on the development computer with real or simulated I/O, or in a third-party simulator. The VI must be under an FPGA target in a LabVIEW project to access this symbol.
      FPGA_TARGET_FAMILYSpecifies to execute different code within an FPGA VI depending on the FPGA family, such as Virtex-II or Virtex-5. The VI must be under an FPGA target in a LabVIEW project to access this symbol.
      OSSpecifies the OS on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
      RUN_TIME_ENGINESpecifies whether the subdiagram executes when you create a LabVIEW stand-alone application or shared library that uses the LabVIEW Run-Time Engine.
      TARGET_BITNESSSpecifies the bitness of the platform on which the subdiagram executes.
      TARGET_TYPESpecifies on which platforms or which targets the subdiagram executes.
      <Custom Symbol>You can define custom symbols in the Conditional Disable Symbols page to add symbols to this list. You also can enter a symbol in the Symbol(s) pull-down menu. If the symbol you enter is not defined in the Conditional Disable Symbols page, an asterisk appears next to the symbol. Both symbols and their valid values are case-sensitive strings.
    • ==/!=—Lists the comparison operators available for use within the expression. Valid comparisons are ==, which specifies that the symbol is equal to the value, and !=, which specifies that the symbol is not equal to the value.
    • Value(s)—Specifies the value of the symbol you select. Value(s) is a case-sensitive string, so you must enter one of the following valid values exactly as it appears below.

      SymbolValid Values
      CPUPowerPC
      x86
      null
      FPGA_EXECUTION_MODE FPGA_TARGET
      DEV_COMPUTER_SIM_IO
      DEV_COMPUTER_REAL_IO
      THIRD_PARTY_SIMULATION
      FPGA_TARGET_FAMILY VIRTEX2
      VIRTEX5
      VIRTEX6
      SPARTAN3
      SPARTAN6
      OS Linux
      Mac
      null
      PharLap
      VxWorks
      Win
      RUN_TIME_ENGINETrue
      False
      TARGET_BITNESS32
      64
      TARGET_TYPEWindows
      FPGA
      Embedded
      RT
      Mac
      Unix
      PocketPC
      DSP
  • Make Default?—Specifies if the current subdiagram is the default subdiagram.

 

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