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Configuring Conditions for Conditional Disable Structures

LabVIEW 2013 Help

Edition Date: June 2013

Part Number: 371361K-01

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A Conditional Disable structure executes one subdiagram depending on the configuration of the condition, which can include the platform and other user-defined symbols.

Complete the following steps to configure conditions for a Conditional Disable structure by selecting symbols and values.

  1. Add a Conditional Disable structure to the block diagram.

  2. (Optional) If you are using the structure in a LabVIEW project, you can create custom conditional disable symbols.
  3. Right-click the structure border and select Edit Condition For This Subdiagram to display the Configure Condition dialog box.
  4. Select a Symbol and enter a Value for the symbol. The following table lists the default symbols and valid values for each symbol. Value is a case-sensitive string, so you must enter one of the following valid values exactly as it appears below.
    SymbolValid ValuesDescription
    CPUPowerPC
    x86
    null
    Specifies the processor on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
    FPGA_EXECUTION_MODEFPGA_TARGET
    DEV_COMPUTER_SIM_IO
    DEV_COMPUTER_REAL_IO
    THIRD_PARTY_SIMULATION
    Specifies to execute different code within an FPGA VI depending on whether the VI executes on the FPGA target, on the development computer with real or simulated I/O, or in a third-party simulator. The VI must be under an FPGA target in a LabVIEW project to access this symbol.
    FPGA_TARGET_FAMILY VIRTEX2
    VIRTEX5
    VIRTEX6
    SPARTAN3
    SPARTAN6
    Specifies to execute different code within an FPGA VI depending on the FPGA family, such as Virtex-II or Virtex-5. The VI must be under an FPGA target in a LabVIEW project to access this symbol.
    OS Linux
    Mac
    null
    PharLap
    VxWorks
    Win
    Specifies the OS on which the subdiagram executes. The VI must be in a LabVIEW project to access this symbol.
    RUN_TIME_ENGINETrue
    False
    Specifies whether the subdiagram executes when you create a LabVIEW stand-alone application or shared library that uses the LabVIEW Run-Time Engine.
    TARGET_BITNESS32
    64
    Specifies the bitness of the instance of LabVIEW or the LabVIEW Run-time Engine that executes the subdiagram.
    TARGET_TYPEWindows
    FPGA
    Embedded
    RT
    Mac
    Unix
    PocketPC
    DSP
    Specifies on which platforms or which targets the subdiagram executes.

    Note  If you do not use the Conditional Disable structure in a LabVIEW project, RUN_TIME_ENGINE, TARGET_BITNESS, and TARGET_TYPE are the only symbols available.
  5. (Optional) Click the plus sign to add another condition. For example, if you want the subdiagram to apply to multiple platforms, such as Windows and Mac, you can set the Value of the TARGET_TYPE symbol to Windows in one condition, click the plus sign, select the OR operator, and set the Value of the TARGET_TYPE symbol to Mac in the second condition.
  6. Click the OK button.
  7. Add objects inside the Conditional Disable structure to create subdiagrams that the Conditional Disable structure can execute. If necessary, add or duplicate subdiagrams.
Note  You can join conditions through Boolean operators to create an expression that allows LabVIEW to evaluate multiple conditions. If more than one condition evaluates to TRUE, the first condition that evaluates to TRUE determines the active subdiagram for the structure. If you define a Boolean expression for a subdiagram, the symbol/value comparisons that you join through the AND operator are evaluated before symbol/value comparisons you join with the OR operator.

If you want to disable a section of code on the block diagram so that it does not compile at run time, use the Diagram Disable structure.

Refer to the Conditional Disable Structure VI in the labview\examples\Structures\Disable Structures directory for an example of using Conditional Disable structures.


 

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