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The LabVIEW Simulation Interface Toolkit ships with bitfiles for many National Instruments R Series Intelligent DAQ devices. These VIs and bitfiles define the analog, digital, and pulse-width modulation (PWM) inputs and outputs of the FPGA device. You use this information to create mappings between a model DLL and one or more FPGA devices. The Simulation Interface Toolkit also ships with a project file you can use with the NI cRIO-9103 chassis.

These default VIs and bitfiles are sufficient for many applications. However, in some situations, you might need to create a custom FPGA VI to use with a simulation. For example, if you want to use additional digital I/O lines, more than two PWM outputs, or digital filtering built into the FPGA, you must create a custom FPGA VI or bitfile. If you are running a simulation on a CompactRIO chassis, you also must create a custom FPGA VI or bitfile, because CompactRIO chassis do not contain any built-in I/O modules. You must install the LabVIEW FPGA Module to create these files.

The following sections provide information about creating a custom FPGA VI and/or bitfile.

Note  This topic assumes you are using a single FPGA device. You can use more than one FPGA device in a simulation, with one of the R Series devices acting as the master device and any other devices acting as slaves. If you use multiple FPGA devices, you must have a bitfile or FPGA VI for each device. Depending on the architecture of the project, you might not need to use a custom FPGA VI for the slave FPGA devices. If the slave devices also need to use a custom FPGA VI, repeat the steps listed in this tutorial for the custom slave FPGA VIs, but instead of starting with the default master FPGA project files, start with the default slave FPGA project files.

Modifying the Default FPGA VI

The first step is to modify a copy of a default FPGA VI. This step is different depending on whether you are using an R Series device or a CompactRIO chassis.

R Series Devices

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
2. Create a copy of sitfpga master.lvproj and place this copy in this same directory.
3. Open this copy in LabVIEW.
4. Expand the RT PXI Target (0.0.0.0) item in the Project Explorer window.
5. Expand the PXI-7831R (PXI-7831R) item in the Project Explorer window.
   
   This example project defines a PXI-7831R device as the target in a real-time (RT) PXI system. If you are using this configuration, proceed to step 6. If you are using a different configuration, you must create a new FPGA target for the device. In this situation, complete the following steps to add a new R Series device to the project.
   1. Right-click the target that controls the R Series device and select New»Targets and Devices from the shortcut menu. If you are using a Windows computer or a Windows-based PXI controller, the controlling target is My Computer. If you are using an RT PXI controller, the controlling target is RT PXI Target (0.0.0.0).
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the device type from the list and click the OK button.
   4. In the Project Explorer window, click and drag sitfpga master.vi from the PXI-7831R (PXI-7831R) target to the new target.
6. Double-click sitfpga master.vi in the Project Explorer window.
7. Select File»Save As from the pull-down menu of the sitfpga master VI window.
8. Ensure the Substitute copy for original option is selected and click the Continue button.
9. Rename the VI and save it to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
10. Save the project by clicking the Save button in the Project Explorer window.

The next step is creating the custom FPGA VI.

CompactRIO Chassis

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
2. Create a copy of sitfpga cRIO master.lvproj and place this copy in this directory.
3. Open this copy in LabVIEW.
4. Expand the FPGA Target (cRIO-9103) item in the Project Explorer window.
   
   This example project defines a cRIO-9103 chassis as the target. If you are using this configuration, proceed to step 6. If you are using a different chassis, you must create a new FPGA target for this chassis. In this situation, complete the following steps to add a new CompactRIO chassis to the project.
   1. Right-click the RT CompactRIO Target (0.0.0.0) item and select New»Targets and Devices from the shortcut menu.
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the CompactRIO chassis type from the list and click the OK button.
   4. In the Project Explorer window, click and drag sitfpga cRIO master.vi and sitfpga cRIO calibration 8_0.llb from the FPGA Target (cRIO-9103) target to the new target.
5. Double-click sitfpga cRIO master.vi in the Project Explorer window.
6. Select File»Save As from the pull-down menu.
7. Ensure the Substitute copy for original option is selected and click the Continue button.
8. Rename the VI and save it to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory.
9. Save the project by clicking the Save button in the Project Explorer window.

The next step is creating the custom FPGA VI.

Creating the Custom FPGA VI

The process of creating the custom FPGA VI differs depending on the hardware devices you are using. Refer to the FPGA Module documentation for information about creating FPGA VIs and bitfiles for an FPGA device.

The default project defines the following FPGA I/O items for the PXI-7831R device: analog input channels 0–7, analog output channels 0–7, and digital lines 0–31 on both connectors 1 and 2. You can add or remove FPGA I/O items depending on the device and the needs of the simulation. For example, the PXI-7811R device has 160 DIO lines available; however, by default this project defines only the first 32 lines on connectors 1 and 2. You can add more FPGA I/O items to this project if you want to use the additional DIO lines available on the PXI-7811R. Conversely, the PXI-7811R has no analog inputs or outputs, so if you are using this device, you can remove the analog I/O items from the project and the corresponding FPGA I/O Nodes from the FPGA VI.

If you created a new target for an R Series device, you can drag the FPGA I/O folders from the original PXI-7831R (PXI-7831R) target to the new target. The FPGA VI shows broken wires from any FPGA I/O Nodes with undefined channels.

CompactRIO Chassis If you are using the existing cRIO-9103 target, the project defines an NI 9215 module for analog input, an NI 9263 module for analog output, an NI 9411 module for digital input, and an NI 9474 module for digital output. You can delete or modify these modules based on the ones you are using for the simulation. If you need to add modules to the target, or if you created a new target, you can add the necessary modules by right-clicking the target and selecting New»C Series Modules.

Note  In the sitfpga cRIO master.vi example, the FPGA itself calibrates the analog input and analog output channels of the NI 9215 and NI 9263 modules. The host VI running on the CompactRIO real-time controller typically performs this calibration. For examples of doing channel calibration on the RT host side rather than on the FPGA itself, refer to the NI-RIO shipping examples Analog Input - cRIO.lvproj and Analog Output - cRIO.lvproj. These examples are available by launching LabVIEW and selecting Help»Find Examples.

Note  Refer to the National Instruments Web site for information about these devices and modules.

While you are creating/modifying the FPGA VI, pay attention to the following guidelines to ensure the SIT Connection Manager dialog box recognizes this FPGA VI.

• Do not remove or rename the input loop, output loop, loop timers, or the _use RTSI Boolean control. Also, do not remove or rename any interrupts the VI uses for host/target synchronization.
• As you create controls and indicators to represent FPGA I/O connections, do not begin the name of these new objects with an underscore. The SIT Connection Manager dialog box ignores any objects with an underscore at the beginning of the name. Conversely, if you want use a control or indicator as an intermediate value, such as those in the PWM I/O loops, prepend an underscore to the name of these objects. This underscore ensures the user does not see the object as available for a mapping.
• Add PWM I/O by copying and renaming an existing PWM control or indicator. For example, the two default PWM input controls are named PWM in 0 (C 0 DIO 0) and PWM in 1 (C 0 DIO 1). A third PWM input must be named PWM in 2 (C connector number DIO DIO line number).
• Do not modify, remove, or rename any objects that are circled in the following figure. However, you can rename or remove the PWM I/O if you do not need them.

The following figure shows the block diagram of sitfpga master.vi.

When you are finished creating the FPGA VI, select File»Save to save this VI.

The next step is compiling the FPGA VI.

Compiling the Custom FPGA VI

Complete the following steps to compile the custom FPGA VI and create the bitfile.

1. Display the Project Explorer window.
2. Right-click the FPGA VI in the tree and select Compile from the shortcut menu to compile the FPGA VI. LabVIEW then creates a bitfile for this VI.
3. Ensure the bitfile is in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\FPGA Bitfiles\ directory. The compiler places the bitfile here automatically if the .lvproj file is located in the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\ directory. By default, the bitfile name is name of project_name of FPGA VI.lvbit.
4. Rename the bitfile according to the rules for naming custom bitfiles.

The next step is using the SIT Connection Manager dialog box to create mappings between the model DLL and the FPGA device.

Using the Custom FPGA VI with the SIT Connection Manager

As you create mappings, you launch the Add FPGA Device dialog box. Use the FPGA Device pull-down list to select the appropriate FPGA device. Then, click the Browse button to specify the custom FPGA bitfile or VI you created. You then can create mappings between the model DLL and the FPGA device using the custom FPGA VI you created.