FPGA devices cannot handle double-precision, floating-point numbers (DBLs). However, Windows computers and real-time (RT) targets often use DBL numbers to perform accurate and precise calculations. To address this compatibility issue, the LabVIEW Simulation Interface Toolkit installs FPGA VIs that represent FPGA I/O connections by using the following data types:
After reading a value from an FPGA input, the driver VI converts these data types to DBL for more accurate processing on a Windows computer or RT target. Before writing a value to an FPGA output, the driver VI converts these data types back into I16, an array of U32s, or Boolean as appropriate. The driver VI does not convert other data types.
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Note The VIs that perform these conversions are located in the labview\vi.lib\addons\Simulation Interface\driversupportVIs\Conversion\ directory. You can eliminate the need for this conversion by configuring the FPGA VI to read and write fixed-point values. The driver VI does not perform any conversion on fixed-point values. |
The following sections describe these conversion processes for each type of FPGA input and output.
By default, the driver VI assumes analog inputs have a range of +/- 10 volts. Therefore, when reading analog inputs, the driver VI converts values received from I16 to DBL by using the following formula:
x * 10 / 32767, where x is the value the driver VI reads from the analog input.
For example, if the driver VI reads a value of 20000 from an analog input, the resulting DBL is 6.1037. The driver VI interprets this value as a reading of 6.1037 volts.
When writing to an analog output, the driver VI converts a DBL to I16 representation by using the formula x * 32767 / 10. For example, when writing a value of 4.3659 volts, the driver VI converts this value to 14306 first.
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Note If you are using analog inputs or outputs with a range different from +/- 10 volts, these conversions are inaccurate. For example, if you are using an analog input with a range of +/- 60 volts, these conversions are inaccurate by a factor of 6. In this situation, you can use a fixed-point number to ensure that the values are converted exactly as you want. |
When reading PWM inputs as arrays of U32s, the driver VI assumes the first two array elements represent the low and high time, respectively, of a PWM signal. The driver VI then converts these values to a DBL between 0.0 and 1.0, where 0.0 represents a 0% duty cycle and 1.0 represents a 100% duty cycle. The driver VI performs this conversion by executing the following steps:
For example consider a situation where a driver VI reads a PWM input of [50000 2000000]. The resulting duty cycle is 0.97561, or 97.561%.
When writing to PWM outputs, the driver VI uses the duty cycle and the specified PWM frequency to produce a 1 x 2 array of U32s, where the first element is the low time and the second element is the high time. The driver VI then writes this array to the PWM outputs.
When reading values from a digital input, the driver VI converts TRUE values to a DBL value of 1.0. The driver VI converts FALSE values to a DBL value of 0.0.
When writing values to a digital output, the driver VI converts any non-zero DBL value to TRUE. The driver VI converts a DBL value of 0.0 to FALSE.
You can use fixed-point values in custom FPGA VIs. The driver VI does not perform any conversion on fixed-point values. The value is directly coerced to a to a double without applying any scaling, which gives you the most control over the scale and range of the value. For cRIO modules with Analog Inputs or Outputs, use the calibrated mode, which returns the values as calibrated and scaled fixed-point values.