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The LabVIEW Simulation Interface Toolkit ships with FPGA bitfiles for many National Instruments R Series Intelligent DAQ devices. These VIs and bitfiles define the analog, digital, and pulse width modulation (PWM) inputs and outputs of the FPGA device. You use this information to create mappings between a model DLL and one or more FPGA devices. The Simulation Interface Toolkit also ships with a project file you can use with the NI cRIO-9103 chassis.

These default bitfiles are sufficient for many applications. However, in some situations, you might need to create a custom FPGA bitfile to use with a simulation. For example, if you want to use additional digital I/O lines, more than two PWM outputs, or digital filtering built into the FPGA, you must create a custom bitfile. If you are running a simulation on a CompactRIO chassis, you also must create a custom bitfile, because CompactRIO chassis do not contain any built-in I/O modules. You must install the LabVIEW FPGA Module to create these files.

The following sections provide information about creating a custom FPGA bitfile.

Creating a custom FPGA bitfile includes the following three steps:

• Make a Copy of the Sample FPGA VI and Project
• Customize the FPGA VI
• Compile the FPGA VI into a Bitfile

Making a Copy of the Sample FPGA VI and Project

The first step is to make a copy of a default FPGA VI and project. This step is different depending on whether you are using an R Series device or a CompactRIO chassis.

R Series Devices

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\Plugins\NI-FPGA\FPGA IO Source\ directory.
2. Create a copy of sit IO.lvproj and place this copy in this same directory.
3. Open this copy in LabVIEW.
4. Expand the My Computer item in the Project Explorer window.
5. Expand the PXI-7831R (PXI-7831R) item in the Project Explorer window.
   
   This example project defines a PXI-7831R device as the target. If you are using this configuration, proceed to step 6. If you are using a different configuration, you must create a new FPGA target for the device. In this situation, complete the following steps to add a new R Series device to the project.
   1. Right-click the target that controls the R Series device and select New»Targets and Devices from the shortcut menu.
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the device type from the list and click the OK button.
   4. In the Project Explorer window, click and drag sitfpga master.vi from the PXI-7831R (PXI-7831R) target to the new target.
   5. Refer to Using the FPGA I/O Node (FPGA Module) for information about adding I/O to the project.
6. Double-click sit IO.vi in the Project Explorer window to open it.
7. Select File»Save As from the pull-down menu of the sit IO VI window.
8. Ensure the Substitute copy for original option is selected and click the Continue button.
9. Rename the VI and save it to the labview\vi.lib\addons\Simulation Interface\_IOTypes\Plugins\NI-FPGA\FPGA IO Source\ directory.
10. Save the project by clicking the Save button in the Project Explorer window.

The next step is customizing the FPGA VI.

CompactRIO Chassis

1. Browse to the labview\vi.lib\addons\Simulation Interface\_IOTypes\Plugins\NI-FPGA\FPGA IO Source\ directory.
2. Create a copy of sitfpga cRIO.lvproj and place this copy in this directory.
3. Open this copy in LabVIEW.
4. Expand the FPGA Target (cRIO-9103) item in the Project Explorer window.
   
   This example project defines a cRIO-9103 chassis as the target. If you are using this configuration, proceed to step 6. If you are using a different chassis, you must create a new FPGA target for this chassis. In this situation, complete the following steps to add a new CompactRIO chassis to the project.
   1. Right-click the RT CompactRIO Target (0.0.0.0) item and select New»Targets and Devices from the shortcut menu.
   2. Select the New target or device option in the Targets and Devices dialog box.
   3. Select the CompactRIO chassis type from the list and click the OK button.
   4. In the Project Explorer window, click and drag sit IO cRIO.vi from the FPGA Target (cRIO-9103) target to the new target.
5. Double-click sit cRIO.vi in the Project Explorer window.
6. Select File»Save As from the pull-down menu.
7. Ensure the Substitute copy for original option is selected and click the Continue button.
8. Rename the VI and save it to the labview\vi.lib\addons\Simulation Interface\_IOTypes\Plugins\NI-FPGA\FPGA IO Source\ directory.
9. Save the project by clicking the Save button in the Project Explorer window.

The next step is customizing the FPGA VI.

Customizing the FPGA VI

The process of creating the custom FPGA VI differs depending on the hardware devices you are using. Refer to the FPGA Module documentation for information about creating FPGA VIs and bitfiles for an FPGA device.

The default project defines the following FPGA I/O items for the PXI-7831R device: analog input channels 0–7, analog output channels 0–7, and digital lines 0–39 on both connectors 1 and 2 and digital line 0—15 on connector 0. You can add or remove FPGA I/O items depending on the device and the needs of the simulation. For example, the PXI-7811R device has 160 DIO lines available; however, by default this sample FPGA VI uses only the first 40 lines on connectors 1 and 2. You can add more FPGA I/O items to this project if you want to use the additional DIO lines available on the PXI-7811R. Conversely, the PXI-7811R has no analog inputs or outputs, so if you are using this device, you can remove the analog I/O items from the project and the corresponding FPGA I/O Nodes from the FPGA VI.

Similarly, the default sample FPGA VI defines the digital lines on connector 0 as 8 PWM inputs and 8 PWM outputs. You might want to more or fewer PWM channels. You might also add other custom I/O not defined in the sample FPGA VI.

Note  The driver VI converts analog, digital, and PWM information to double-precision, floating-point numbers for greater accuracy and precision on Windows computers and RT targets. You can avoid this conversion by creating an FPGA VI that transmits this information by using fixed-point numbers. For more information about how SIT handles data types on FPGA, refer to Representing Data Types on FPGA Devices.

If you created a new target for an R Series device, you can drag the FPGA I/O folders from the original PXI-7831R (PXI-7831R) target to the new target. The FPGA VI shows broken wires from any FPGA I/O Nodes with undefined channels.

(CompactRIO Chassis) If you are using the existing cRIO-9103 target, the project defines an NI 9215 module for analog input, an NI 9263 module for analog output, an NI 9411 module for digital input, and an NI 9474 module for digital output. You can delete or modify these modules based on the ones you are using for the simulation. If you need to add modules to the target, or if you created a new target, you can add the necessary modules by right-clicking the target and selecting New»C Series Modules.

Note  In the sit cRIO.vi example, the FPGA I/O mode calibrates the analog input and analog output channels of the NI 9215 and NI 9263 modules. The host VI running on the CompactRIO real-time controller returns the data as a scaled fixed-point vaue.

Note  Refer to the National Instruments Web site for information about these devices and modules.

While you are creating/modifying the FPGA VI, pay attention to the following guidelines to ensure the SIT Connection Manager dialog box recognizes this FPGA VI.

• Do not modify, remove, or rename any objects in the gray areas of the sample FPGA VI.
• As you create controls and indicators to represent FPGA I/O connections, do not begin the name of these new objects with an underscore or asterisk. The SIT Connection Manager dialog box ignores any objects with an underscores or asterisks at the beginning of the name. Conversely, if you want use a control or indicator as an intermediate value, such as those in the PWM I/O loops, prepend an underscore to the name of these objects. This underscore ensures the user does not see the object as available for a mapping.
• Do not use the following control indicator names : Loop Rate (used), Loop Rate (ticks), Late? Latched, Reset, Start 0, Local Stop 0, _IRQ Bit (0—31), _Master3, _use RTSI).
• Add PWM I/O by copying and renaming an existing PWM control or indicator. For example, the two default PWM input controls are named PWM in 0 (C 0 DIO 0) and PWM in 1 (C 0 DIO 1). A third PWM input must be named PWM in 2 (C connector number DIO DIO line number ).
• National Instruments recommends that you start control names with AI for analog in, AO for analog out, and so on.

When you are finished creating the FPGA VI, select File»Save to save this VI.

The next step is compiling the custom FPGA VI into a bitfile.

Compiling the Custom FPGA VI into a Bitfile

Complete the following steps to compile the custom FPGA VI and create the bitfile.

1. Display the Project Explorer window.
2. Right-click the FPGA VI in the tree and select Compile from the shortcut menu to compile the FPGA VI. LabVIEW then creates a bitfile for this VI.
3. Copy the resulting bitfile to the labview\vi.lib\addons\Simulation Interface\_IOTypes\NI FPGA\FPGA IO VIs\FPGA Bitfiles\ directory. The compiler places the bitfile in a subdirectory, FPGA Bitfiles,relative to the project file directory. By default, the bitfile name is name of project_name of FPGA VI .lvbit.
4. Rename the bitfile according to the rules for naming custom bitfiles.

The next step is using the SIT Connection Manager dialog box to create mappings between the model DLL and the FPGA device.

Using the Custom FPGA VI with the SIT Connection Manager

As you create mappings, you associate the custom FPGA bitfile you created with the appropriate FPGA device. You then can create mappings between the model DLL and the FPGA device using the custom FPGA VI you created.

Tip   If the bitfile does not show up, it is likely that it does not follow the naming conventions listed above or that it is not in the correct directory.