Configuration/Powerup Considerations for USB R Series Digital Line Voltage Levels

NI R Series Multifunction RIO Device Drivers Help

Edition Date: May 2018

Part Number: 371508V-01

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There is a switching time that you need to accommodate for when configuring the voltage level of a digital line to avoid reading incorrect data or temporarily outputting an unexpected voltage. Do not set the logic family for the DIO while reading from or writing to a digital line. Refer your USB R Series device specification document for more information about switching time.

There is also a switching time for the voltage level of a digital line during powerup. The digital line is at 1.2 V during powerup. The USB R Series device will ramp up to the selected logic family voltage and the DIO can start executing in a single-cycle timed loop before the ramp up is complete.

You can use one of the following methods to accommodate for the switching time when configuring the voltage level or during powerup.

  • Wait the maximum amount of switching time before reading from or writing to a digital line.
  • Read the FPGA I/O Node error terminal for error codes 62000 or 62001. Complete the following steps to read the error terminal.
    1. Place an FPGA I/O Node for the digital line inside a single-cycle timed loop on the block diagram.
    2. Right-click the FPGA I/O Node and select Show Error Terminals.
    3. Place an Unbundle By Name function on the block diagram.
    4. Wire the error out terminal on the FPGA I/O Node to the Unbundle By Name function.
    5. Click the Unbundle By Name function and select code.
    6. Place a Not Equal to 0? function on the block diagram.
    7. Wire the Unbundle By Name function to the Not Equal to 0? function.
    8. Wire the Not Equal to 0? function to the loop condition of the single-cycle timed loop.

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