NI USB-7846R OEM Reference

NI R Series Multifunction RIO Device Drivers Help

Edition Date: May 2018

Part Number: 371508V-01

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R Series Reconfigurable OEM I/O Module (AI, AO, DIO)

8 AI channels, 8 AO channels, 48 DIO channels, Kintex-7 K160T FPGA, 500 kS/s AI Sample Rate

FPGA I/O Node

You can use an FPGA I/O Node, configured for reading and writing, with this device.

Note  FPGA I/O Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line.

Terminals in Software

You can select the following terminals for this device.

Terminal Description
AIx Analog input channel x, where x is the channel number. Use an FPGA I/O Node configured for reading to access this channel.
AOx Analog output channel x, where x is the channel number. Use an FPGA I/O Node configured for writing to access this channel.
Connectorx/DIOy Digital input/output channel y on connector x, where y is the channel number and x is the connector number. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this channel.
Connectorx/DIOPORTy Digital input/output port y on connector x, where y is the port number and x is the connector number. A port is made up of eight digital channels. Use an FPGA I/O Node configured for reading or writing, or use the Set Output Data or Set Output Enable method to access this port.
Board IO/Device Temperature Returns the current temperature of the device, in increments of 0.25 °C. The temperature is measured from an onboard temperature sensor on the device PCB, external to the FPGA.
Board IO/FPGA Temperature Returns the current temperature of the FPGA, in degrees Celsius.
Board IO/UserLED1 Controls the User LED1 on the module. Set the User LED1 terminal to TRUE to turn the LED on and FALSE to turn the LED off.
Board IO/UserLED2 Controls the User LED2 on the module. Set the User LED2 terminal to TRUE to turn the LED on and FALSE to turn the LED off.
Board IO/UserLED3 Controls the User LED3 on the module. Set the User LED3 terminal to TRUE to turn the LED on and FALSE to turn the LED off.

Arbitration

This device supports arbitration. Configure the arbitration settings for the channels of this device in the FPGA I/O Properties dialog box for the FPGA I/O item you are using.

I/O Methods

Use the FPGA I/O Method Node to invoke methods. You can use the following methods with this device.

Note  FPGA I/O Method Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line.

Method Description
Set Output Data Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.
Set Output Enable Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.
Wait on Any Edge Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Falling Edge Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on High Level Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Low Level Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Rising Edge Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.

I/O Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Property Description
LSB Weight Returns the gain calibration coefficient for an analog output channel.
LSB Weight (±1 V Range) Returns the gain calibration coefficient for the ±1 V range of an analog input channel.
LSB Weight (±2 V Range) Returns the gain calibration coefficient for the ±2 V range of an analog input channel.
LSB Weight (±5 V Range) Returns the gain calibration coefficient for the ±5 V range of an analog input channel.
LSB Weight (±10 V Range) Returns the gain calibration coefficient for the ±10 V range of an analog input channel.
Offset Returns the offset calibration coefficient for an analog output channel.
Offset (±1 V Range) Returns the offset calibration coefficient for the ±1 V range of an analog input channel.
Offset (±2 V Range) Returns the offset calibration coefficient for the ±2 V range of an analog input channel.
Offset (±5 V Range) Returns the offset calibration coefficient for the ±5 V range of an analog input channel.
Offset (±10 V Range) Returns the offset calibration coefficient for the ±10 V range of an analog input channel.
Voltage Range Sets the input range for an AI channel as ±10 V, ±5 V, ±2 V, or ±1 V. This property overwrites the value you configure in the Configure R Series I/O dialog box.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Property Description
AI Terminal Mode Sets the terminal mode for a channel as RSE (referenced single-ended), NRSE (non-referenced single-ended ), or DIFF (differential). This property overwrites the value you configure in the Configure R Series I/O dialog box.
Connector1:2 DIO Logic Family Sets the logic family for the DIO on connector1 and connector2 as 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V. This property overwrites the value you configure in the Configure R Series I/O dialog box.
Connector3 DIO Logic Family Sets the logic family for the DIO on connector3 as 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V. This property overwrites the value you configure in the Configure R Series I/O dialog box.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only.

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