Using FIFOs in FPGA VIs (FPGA Module)

Complete the following steps to add a local or DMA FIFO to an FPGA VI.

1. Create a new project or open an existing project.
2. Add an FPGA target to the project.
3. Add an FPGA FIFO to the project.
4. Place a FIFO Read or FIFO Write function on the block diagram.
   
   FIFO Read
   
   
   
   FIFO Write
   
   
5. Right-click the FIFO Read or FIFO Write function and select Select FIFO»x from the shortcut menu, where x is the name of the FPGA FIFO item in the Project Explorer window.

You also can click the FPGA FIFO item in the Project Explorer window and drag it onto the block diagram. If you click a local FIFO and drag it onto the block diagram, LabVIEW places a FIFO Read function, configured for the local FIFO, onto the block diagram. If you click a DMA FIFO and drag it onto the block diagram, LabVIEW places a FIFO Write function, configured for the DMA FIFO, on the block diagram.

Note  If you use the the functions in a single-cycle Timed Loop, you must wire a constant of zero to the Timeout parameter of the FIFO Read and FIFO Write functions.

Refer to Reading DMA FIFOs from Host VIs for more information about using DMA FIFOs in host VIs.

 

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