Reading DMA FIFOs from Host VIs (FPGA Interface)

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You can create Direct Memory Access (DMA) FIFOs in FPGA VIs, which you then can read in host VIs. The FPGA targets that support DMA include a fixed number of DMA channels available for transferring data from the FPGA VI to the host VI. You can use only one FIFO for each DMA channel. Refer to the specific FPGA target hardware documentation for information about the number of DMA channels available.

Complete the following steps to read a DMA FIFO in an FPGA VI.

Open a reference to an FPGA VI or bitfile.

Note The FPGA target, FPGA VI, and host VI must be in the same LabVIEW project if you want to open a reference to an FPGA VI. The host VI does not need to be in a project if you open a reference to a bitfile. If you open a reference to an FPGA VI, the project must include a DMA FIFO item under the FPGA target and the FPGA VI must include a FIFO Write function on the block diagram that writes to the DMA FIFO item.

Place an Invoke Method function on the block diagram of the host VI in the data flow where you want the host VI to read the DMA FIFO. Make sure the host VI runs the FPGA VI before you read the DMA FIFO. Wire the FPGA VI Reference In input.
Click the Invoke Method function and select FIFO»Read from the shortcut menu, where FIFO is the name of the FIFO item in the project. Wire the inputs and outputs as needed. The Read method returns Data when the Number of Elements is available or when the Timeout period ends. If the Timeout period ends before the Number of Elements is available, Data will be empty. The Elements Remaining output contains the number of elements remaining in the host memory part of the DMA FIFO.

Note You can read DMA FIFOs using only the Invoke Method function with the Read method, but you also can configure, start, and stop the DMA FIFO using the Invoke Method function if you want more control over the DMA FIFO from the host VI.

Reading DMA FIFOs from Host VIs (FPGA Interface)

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