What's New in LabVIEW 8.0 FPGA Module

LabVIEW 8.0 features and changes
FPGA Module 8.0 Features
Upgrading to the LabVIEW FPGA Module 8.0

Refer to the readme_fpga.html file in the LabVIEW 8.0\readme directory for information about known issues.

FPGA Module 8.0 Features

The FPGA Module 8.0 includes the following new features to help you better manage and implement the components of an FPGA application: FPGA targets, FPGA VIs, host VIs, and target-specific options. The FPGA VI is the VI you create to run on an FPGA target and define the functionality of the target. The host VI is the VI you create to run in Windows or on an RT target and communicate with the FPGA VI on the FPGA target. You can run only one FPGA VI on an FPGA target at a time.

Managing FPGA Targets and VIs in LabVIEW Projects

LabVIEW 8.0 features the new Project Explorer window and the LabVIEW project to manage applications that include multiple VIs and resources, such as FPGA targets. The FPGA Module 8.0 uses the Project Explorer window to manage the components of an FPGA application, including FPGA VIs, host VIs, FPGA targets, and target-specific options, such as FPGA I/O, FPGA FIFOs, and FPGA clocks. The Project Explorer window surpasses the functionality of the Embedded Project Manager window in the FPGA Module 1.1. You now can manage all the components of an FPGA application, including FPGA VIs and host VIs, in a single project.

You must create projects to create FPGA VIs. Click the Empty Project link in the Getting Started window to create an empty project. Use the Real-Time Project Wizard, available by selecting Real-Time Project from the Targets pull-down menu in the Getting Started window, if you want to create a new project that includes an RT target and VIs ready to deploy to the RT target. You then can right-click My Computer or the RT target in the Project Explorer window and select New»Targets and Devices from the shortcut menu to add an FPGA target to the project.

Adding I/O to the Project

You can add FPGA I/O to a project by right-clicking an FPGA target in the Project Explorer window and selecting New»FPGA I/O from the shortcut menu. You can determine the I/O resources on the FPGA target that you want to use, and you then can assign unique names to the I/O resources you use.

To use the FPGA I/O you configure in the Project Explorer window in an FPGA VI, first place an FPGA I/O Node on the block diagram of an FPGA VI under the same FPGA target in the Project Explorer window. To configure the FPGA I/O Node to perform the I/O operations you created in the Project Explorer window, click the I/O Name terminal in the FPGA I/O Node and select an I/O resource you configured from the shortcut menu. You also can drag an FPGA I/O item from the Project Explorer window onto the block diagram to drop a configured FPGA I/O Node on the block diagram. You no longer need to select from a few pre-defined FPGA Device I/O functions on the palette.

Some I/O resources, such as digital input/output lines, allow you to change read or write behavior from the shortcut menu of the FPGA I/O Node. Right-click the FPGA I/O Node after you configure it for digital input or output and select Change to Write from the shortcut menu if you want to write to the I/O resource or Change to Read from the shortcut menu if you want to read the I/O resource.

You can put inputs and outputs, analog and digital, all in the same node on the block diagram. You can set target-specific properties and call methods on the FPGA I/O items with the FPGA I/O Property Node and the FPGA I/O Method Node, respectively. Some FPGA targets allow you to select I/O, PXI, and RTSI resources. Other FPGA targets allow you to select resources in the FPGA on the device that provide fixed features designed by National Instruments. Refer to the specific FPGA target hardware documentation for more information.

Using Direct Memory Access with FPGA FIFO Functions

The FPGA Module 8.0 includes direct memory access (DMA) support with the new DMA transfer type of the FIFO Operations functions. Use the DMA FIFOs to transfer large amounts of data quickly from the FPGA target to the host computer.

Create DMA FIFOs for the FPGA VI in the Project Explorer window by right-clicking the FPGA target and selecting New»FIFO from the shortcut menu. In the FPGA FIFO Properties dialog box that appears, select DMA from the Type pull-down menu. You then can use the FIFO Operations functions in the FPGA VI. Retrieve data from the DMA FIFO in the host VI with the Invoke Method function calling one of the DMA FIFO methods. You cannot write data to the DMA FIFOs from the host VI.

Some targets might not support the DMA FIFOs. Refer to the specific FPGA target hardware documentation for information about supported features.

Using Multiple Clock Domains

The FPGA Module 8.0 allows multiple clocks within a single FPGA VI. In the FPGA Module 1.1, you can use only one global clock. You now can use multiple clocks to partition an FPGA VI into sections of code that run at different clock rates. You can use higher clock rates for applications such as pulse width measurement and pulse generation where the speed of the loop directly impacts the resolution of the measurement or generation.

All FPGA targets include an FPGA base clock in the Project Explorer window. You also can create derived clocks by right-clicking the base clock in the Project Explorer window and selecting New FPGA Derived Clock from the shortcut menu. You also can specify that a single-cycle Timed Loop use a clock you created as the timing source in the Configure Timed Loop dialog box, available by double-clicking the Input Node of the Timed Loop. To set a top-level clock for the FPGA VI, right-click the FPGA target in the Project Explorer window and select Properties from the shortcut menu. Then select the Top-Level Clock category and select a clock from the Configured Clock list.

Support for multiple clock domains varies by FPGA target. Refer to the specific FPGA target hardware documentation for information about multiple clock domain support and usage.

Saving the Compiled FPGA Code in a Separate File

LabVIEW now saves the code generated during compilation of an FPGA VI, or bitfile, in a file separate from the FPGA VI. You can open a reference to a specific bitfile from host VIs with the Open FPGA VI Reference function for Programmatic FPGA Interface Communication. If you do not have the FPGA Module, you must open a reference to the specific bitfile.

National Instruments recommends you open a reference to the FPGA VI rather than a specific bitfile for most applications. You must include the host VI in the same LabVIEW project as the FPGA VI if you open a reference to an FPGA VI. If you open a reference to a bitfile, you do not need to include the host VI in a project.

Binding FPGA VI Reference Out Parameters to Type Definitions

In the FPGA Module 1.x, you cannot bind the FPGA VI Reference Out parameter of the Open FPGA VI Reference or Up Cast function to type definitions, which makes it difficult to use subVIs in the host VI. You now can bind the FPGA VI Reference Out parameter of the Open FPGA VI Reference or Up Cast function to type definitions so that LabVIEW automatically propagates configuration changes to subsequent subVIs in the data flow.

Some targets might not support the Up Cast function. Refer to the specific FPGA target hardware documentation for information about supported features.

Using Interactive Front Panel Communication and FPGA Target Emulators

The FPGA Module 8.0 supports many new National Instruments hardware targets. All NI FPGA targets include support for Programmatic FPGA Interface Communication. Some FPGA targets also include support for Interactive Front Panel Communication. A subset of the FPGA targets that support Interactive Front Panel Communication include support for FPGA target emulators. Refer to the specific FPGA target hardware documentation for information about whether the target supports Interactive Front Panel Communication or an FPGA target emulator.

If the target supports an FPGA target emulator, you can specify that VIs under the target in the Project Explorer window run with the FPGA target emulator in the FPGA Target Properties dialog box, available by right-clicking the FPGA target in the Project Explorer window and selecting Properties from the shortcut menu.

Programmatically Aborting and Resetting FPGA VIs

In the FPGA Module 1.x, LabVIEW aborts and resets the FPGA VI when you use the Invoke Method function with the Abort method in the host VI. In the FPGA Module 8.0, LabVIEW only aborts the FPGA VI without resetting the FPGA VI when you use the Invoke Method function with the Abort method. You must use the Invoke Method function with the new Reset method if you want to abort and reset the FPGA VI.

What's New in LabVIEW 8.0 FPGA Module

FPGA Module 8.0 Features

Managing FPGA Targets and VIs in LabVIEW Projects

Adding I/O to the Project

Using Direct Memory Access with FPGA FIFO Functions

Using Multiple Clock Domains

Saving the Compiled FPGA Code in a Separate File

Binding FPGA VI Reference Out Parameters to Type Definitions

Using Interactive Front Panel Communication and FPGA Target Emulators

Programmatically Aborting and Resetting FPGA VIs

Upgrading to the LabVIEW FPGA Module 8.0

FPGA Device I/O Functions

Embedded Project Manager

Upgrading FPGA VIs, Host VIs, and Embedded Projects from the LabVIEW FPGA Module 1.x to 8.0

Resources