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FPGA Module Concepts



Creating Custom Hardware from LabVIEW

Additional Advantages of the FPGA Module
FPGA Module Application Development

Creating FPGA VIs

Configuring and Accessing Remote FPGA Targets
Managing FPGA Applications in the Project Explorer Window
Performing Basic FPGA I/O
Timing FPGA VIs
Executing Code in a Single FPGA Target Clock Cycle
Changing the Top-Level FPGA Target Clock Rate
Customizing I/O
Using Parallel Operations
Understanding How to Program FPGA VIs
Controlling I/O Power-On States
Communicating with a Host VI
Importing HDL Code into FPGA VIs

Defining Inputs and Outputs on the HDL Interface Node
Execution Control and Enable Chain Signals for HDL Code
Controlling Execution of the HDL Interface Node
Writing HDL Code to Adapt to Multiple Clock Rates
Including External HDL Code in the HDL Interface Node

Optimizing FPGA VIs for Speed and Size

Reducing Combinatorial Paths in FPGA VIs
Using Single-Cycle Timed Loops to Optimize FPGA VIs
Avoiding Arbitration to Optimize FPGA VIs
Limiting the Number of Front Panel Objects in FPGA VIs
Using the Smallest Data Type to Optimize FPGA VIs
Avoiding Large VIs and Functions in FPGA VIs When Possible

Managing Shared Resources, Contention, and Arbitration

Understanding Arbitration Options
Avoiding Jitter Due to Resource Contention
Timing with Arbitration Enabled

Running FPGA VIs

Using the LabVIEW FPGA Compile Server
Downloading Compiled FPGA VIs to the FPGA Target
Running Compiled FPGA VIs