FPGA Module How-To
Adding FPGA Targets to a LabVIEW Project
Setting Access Permissions for Remote FPGA Targets
Verifying Communication with Remote FPGA Targets
Upgrading FPGA VIs, Host VIs, and Embedded Projects from LabVIEW FPGA Module 1.x to 8.2 (FPGA Module)
Using FPGA Targets in a LabVIEW Project
Adding Items to an FPGA Target in the Project Explorer Window
Configuring FPGA Targets
Reusing FPGA VIs and FPGA Items among Multiple FPGA Targets
Viewing Bitfile Path for FPGA VIs
Changing Arbitration Options
Synchronizing FPGA VIs and Host VIs Using Interrupts
Managing FPGA Clocks and Timing
Adding an FPGA Base Clock to a LabVIEW Project
Configuring FPGA Base Clocks
Creating FPGA Derived Clocks
Configuring FPGA Derived Clocks
Selecting a Top-Level Clock for an FPGA Target
Controlling the FPGA VI Execution Rate
Selecting an FPGA Clock as the Timing Source for a Single-Cycle Timed Loop
Forcing VI Execution at a Specific Time Interval
Measuring While Loop Execution Rate
Creating FPGA FIFOs
Using FIFOs in FPGA VIs
Creating Memory Items
Using Memory Items in FPGA VIs
Creating New FPGA I/O Items
Configuring FPGA I/O Items
Using the FPGA I/O Node
Using FPGA I/O Method Nodes
Using FPGA I/O Property Nodes
Creating Fixed-Size Arrays
Returning Fixed-Size Arrays from Array Functions
Compiling FPGA VIs
Compiling an FPGA VI Remotely
Disconnecting from the LabVIEW FPGA Compile Server while Compiling
Configuring FPGA VIs to Run Automatically
Downloading an FPGA VI to the Flash Memory of an FPGA Target
Debugging Techniques for FPGA VIs
Adding I/O to Monitor FPGA VIs
Adding Indicators to Monitor FPGA VIs
Running an FPGA VI with an FPGA Target Emulator
Emulation VI broken
Emulation VI interface doesn't match HDL Input node interface
Emulation VI not available
Enable chain handled incorrectly
Inputs/outputs unconfigured