You are here: NI Home > Support > Product Reference > Manuals > LabVIEW FPGA Module 8.2 Help

Implements an integer PID algorithm for simple PID applications or high-speed control applications that require an efficient algorithm. The PID algorithm features control output range limiting with integrator anti-windup. The PID algorithm also features bumpless controller output for PID gain changes. Details  

	initialize, when TRUE, sets the derivative (D) action to zero and resets the integrated error to zero. The VI initializes automatically when it first runs.
	setpoint is the value that you want the process variable to attain.
	process variable is the value of the variable that you are controlling.
	PID gains (x 2^8) is a cluster of three integers representing the scaled PID gain parameters. The upper 8 bits of each integer represent the integer portion of the gain, and the lower 8 bits of each integer represent the fractional portion of the gain. proportional gain (Kc) represents the proportional (P) gain of the controller. integral gain (Kc*Ts/Ti) represents the integral (I) gain of the controller. Ts represents the sampling interval, in minutes. Ti represents the integral time, in minutes. derivative gain (Kc*Td/Ts) represents the derivative (D) gain of the controller. Td represents the derivative time, in minutes. Ts represents the sampling interval, in minutes.
	output range is the allowable range of the integer output. The VI also uses the integrator anti-windup calculation to limit the effect of the integral action during transients. output high is the maximum value of output. output low is the minimum value of output.
	output is the control signal returned by the PID algorithm. where PV(n) = value of process variable on the nth call after initialization ΔPV(n) = PV(n) – PV(n – 1) e(n) = setpoint(n) – PV(n) Ts = sampling interval P = Kc I = Ki * Ts D = Kd / Ts Ki = Kc / Ti Kd = Kc * Td Ti and Td are the integral and derivative times, respectively, in minutes, and Kc is the proportional gain constant.

Discrete PID Details

The Discrete PID VI uses saturation arithmetic and internal scaling to avoid integer overflow. All scaling rounds to negative infinity.

Compute the PID gains (x 2^8) inputs before you pass them into an FPGA VI. You can compute the required integer gain values in a host VI and pass them to a PID loop running on the FPGA target.