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Reads the oldest element in an FPGA FIFO and removes the element from the FIFO. Details  

	Timeout inputs the number of clock ticks the function waits for available data in the FIFO if the FIFO is empty. The default is 0, or no wait. A value of –1 prevents the function from timing out, so the function completes execution only when data is available for reading.
	Element returns the oldest data element in the FIFO. The Element data type is the data type you configure in the FPGA FIFO Properties dialog box when you create the FIFO.
	Empty returns TRUE if an element is not available in the FIFO before the function completes execution. If Empty is TRUE, Element is undefined.

FIFO Read Details

To read from or write to FIFOs with the FIFO Read and FIFO Write functions, you must create FIFO items. You can create a FIFO item in the Project Explorer window or using the VI-Scoped FIFO Configuration node. You then can right-click the FIFO Read or FIFO Write function and select the FIFO item from the Select FIFO shortcut menu.

Tip  You can click a FIFO item in the Project Explorer window and drag it onto the block diagram to place a FIFO Read or FIFO Write function on the block diagram.

Right-click the FIFO Read function and select Add New FIFO from the shortcut menu to create a new target-scoped or DMA FIFO.

When you run the FPGA VI with an FPGA target emulator, FIFOs reset when the VI stops and then starts again. When you run the FPGA VI on an FPGA target using Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI stops and then starts again. To reset FIFOs, right-click the FPGA target in the Project Explorer window and select Reset from the shortcut menu. To reset FIFOs when you control an FPGA VI using Programmatic FPGA Interface Communication, use the Invoke Method function with the Reset method or the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected.

Add error terminals to be sure the data you receive is valid. Right-click the FIFO Read function on the block diagram and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. If error in includes an error, you might receive incorrect data.

Note  Adding error in and error out parameters increases the amount of space the function uses on the FPGA target. The error in and error out parameters also can cause slower execution on the FPGA target.

Special Considerations for Single-Cycle Timed Loops

If you use the FIFO Read function in a single-cycle Timed Loop, you must set the Read option in the FPGA FIFO Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate for the FIFO item you read, and you cannot use the function with that FIFO anywhere else in the FPGA VI. You also must wire a constant of 0 to Timeout.

You can use FIFOs to transfer data among multiple clock domains.