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Repeats the subdiagram inside it every clock cycle of the configured FPGA clock until the conditional terminal, an input terminal, receives a particular Boolean value. Use the single-cycle Timed Loop as you do a While Loop. You also can use the single-cycle Timed Loop to implement multiple clock domains in an FPGA VI. Double-click the Input Node to display the Configure Timed Loop dialog box in which you can specify the FPGA target clock you want to use.

You can use most VIs and functions available when you target an FPGA target in a single-cycle Timed Loop. However, you cannot use the following VIs, functions, and structures in a single-cycle Timed Loop. LabVIEW reports a code generation or compile-time error for the single-cycle Timed Loop when you try to compile an FPGA VI with any of the following VIs, functions, or structures in a single-cycle Timed Loop.

• For Loop
• FPGA Math & Analysis VIs except the Linear Interpolation, Look-Up Table 1D, and Saturation Arithmetic VIs
• FPGA I/O Method Node except with some FPGA targets
• FPGA I/O Property Node except with some FPGA targets
• Interrupt VI
• Loop Timer VI
• Quotient & Remainder function
• Rotate 1D Array function
• Timed Loop
• Wait Express VI
• Wait on Occurrence function
• While Loop
• Multiple FPGA I/O Nodes configured for the same I/O resource if at least one node is inside the loop and at least one node is outside the loop
• Non-reentrant subVIs if you use multiple instances

The FPGA target you use might not support additional VIs or functions. Also, some targets do not support specific I/O items both inside and outside a single-cycle Timed Loop. Refer to the specific FPGA target hardware documentation for more information.

The inputs that appear in the Input Node of the Timed Loop have no effect when you use the loop in an FPGA VI.

Note  Do not add frames before or after the single-cycle Timed Loop frame to try to use the single-cycle Timed Loop as a Timed Sequence structure in an FPGA VI. The LabVIEW FPGA Module does not support Timed Sequence structures.

You can place indicators in the single-cycle Timed Loop only if you do not have any local variables writing to the indicators.

You can use the FPGA I/O Node in the single-cycle Timed Loop if the FPGA target allows it. Refer to the specific FPGA target hardware documentation to determine whether the target supports FPGA I/O Nodes in the single-cycle Timed Loop. If the FPGA target you use supports the single-cycle Timed Loop, you can use only the Arbitrate if Multiple Requestors Only and Never Arbitrate arbitration options. If you select Arbitrate if Multiple Requestors Only, you cannot use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI. If you select Never Arbitrate, you can use more than one instance of the FPGA I/O Node for a specific I/O item in the FPGA VI if each instance is in a single-cycle Timed Loop executing at the same rate.

You can use the Flat Sequence or Stacked Sequence structure in the single-cycle Timed Loop. However, all sequence frames execute in one clock cycle.

You cannot use more than one instance of a non-reentrant or shared subVI in a single-cycle Timed Loop. You can use reentrant VIs if all instances of the reentrant VI in the FPGA VI occur in the single-cycle Timed Loop.

You cannot use the Wait on Occurrence function in a single-cycle Timed Loop. However, you can use the Set Occurrence function. You then can use the Wait on Occurrence function outside the single-cycle Timed Loop in a While Loop or For Loop.

You can use some functions in the single-cycle Timed Loop that take one clock cycle to execute, such as the Memory Read VI. Wire the outputs of such functions directly to uninitialized shift registers because the output data is not valid until the next iteration of the single-cycle Timed Loop.

Understanding the Implementation of the Timed Loop on FPGA Targets

The single-cycle Timed Loop is similar to a clocked process in VHDL. The shift registers, digital output functions, and indicators are registers enabled by the conditional terminal in the single-cycle Timed Loop. All other LabVIEW code in the single-cycle Timed Loop is combinatorial logic on the FPGA target. Inputs to the combinatorial logic are outputs from components such as digital input functions, controls, or left shift registers.

Flip-flops and combinatorial logic enable the execution of LabVIEW on FPGAs. Flip-flops are synchronization elements that hold the output constant between edges of a global clock Flip-flops have a D input, an enable input, a clock input, and a Q output. The D input is transferred to the Q output on any clock edge during which the enable is asserted. The Q output of a flip-flop feeds combinatorial logic such as look-up tables, AND gates, and MUXs. Static timing analysis during a compilation guarantees that a new value on the Q output of a flip-flop propagates through all combinatorial logic and is ready to be sampled by a receiving the flip-flop D input before the next clock edge. If any combinatorial path exceeds the period of the global clock, LabVIEW returns the Compilation Failure dialog box when you try to compile the FPGA VI.

With the single-cycle Timed Loop, shift registers map directly to flip-flops and logic inside the loop maps directly to combinatorial logic. The inside left terminal of the shift register is the Q output of a flip-flop or bank of flip-flops commonly referred to as a register, and the inside right terminal of a shift register is the D input to a flip-flop or bank of flip-flops. The single-cycle Timed Loop maps to a circuit as shown in the following schematic diagram.