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Owning Palette: Structures

Use the Timed Loop structure to control the rate at which a subdiagram executes.

Note  This palette is specific to FPGA targets and contains a subset of the VIs and functions that are on this palette when you edit a Windows or RT target VI.

Palette Object	Description
Timed Loop	Repeats the subdiagram inside it every clock cycle of the configured FPGA clock until the conditional terminal, an input terminal, receives a particular Boolean value. Use the single-cycle Timed Loop as you do a While Loop. You also can use the single-cycle Timed Loop to implement multiple clock domains in an FPGA VI.