You are here: NI Home > Support > Product Reference > Manuals > LabVIEW FPGA Module 8.2 Help

Owning Palette: FPGA Math & Analysis VIs

Use the Utilities VIs in FPGA VIs to perform various tasks such as detecting state changes of Boolean inputs, detecting zero crossings, delaying the input value, limiting the valid range of a signal, and performing linear interpolation.

Note  This palette is specific to FPGA targets.

Palette Object	Description
Boolean Crossing	Detects state changes of Boolean input points. You can choose from three detectors: either, false-true, or true-false.
Discrete Delay	Delays the input value for the number of loop iterations you specify in the Configure Discrete Delay dialog box.
Linear Interpolation	Performs linear interpolation to approximate a function evaluation at an arbitrary location in an interval between two known points.
Saturation	Limits the valid range of a signal to that specified by Upper limit and Lower limit. You can configure the VI to specify the integer or bit limits and signed or unsigned inputs.
Unit Delay	Delays the input value for one cycle.
Zero Crossing	Detects zero crossings of an integer input signal.