HDL Interface Node (FPGA Module)

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LabVIEW FPGA Module 8.2 Help
August 2006

NI Part Number:
371599B-01

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Allows you to use VHDL code in an FPGA VI. Double-click the HDL Interface Node on the block diagram to display the HDL Interface Node Properties dialog box. You configure all the inputs, outputs, internal functionality, external reference files, and so on in the HDL Interface Node Properties dialog box. Refer to the Importing HDL Code into FPGA VIs topic for information about using the HDL Interface Node in FPGA VIs.

Dialog Box Options

Dialog Box Options

Parameter

Description

Parameters

Contains the following options:

Parameters—Defines and configures inputs and outputs to the HDL Interface Node. The Parameters table contains the following options:
- Name—Displays the name of the parameter that appears in the HDL Interface Node on the block diagram. Double-click the cell to enter or edit a parameter name.
- Direction—Defines if the parameter is an input or output. Click the cell to select Input or Output.
- Type—Defines the data type of the parameter. LabVIEW displays only a subset of the data types supported in FPGA VIs. Click the cell to select a data type. If you select the Boolean array data type, you must enter a Length.
- Length—Defines the size of the Boolean array if you select the Boolean array data type in the Type column. Click the cell to enter the Length.
Import From VI—Displays the Import From VI dialog box. Select a VI from the Import From VI dialog box to import into the HDL Interface Node. LabVIEW sets the parameters of the HDL Interface Node to be the controls and indicators on the connector pane of the selected VI. The HDL Interface Node replaces any parameters you have already entered.
Export To VI—Displays the Export To VI dialog box. Select a VI from the Export To VI dialog box to which to export the HDL Interface Node parameters. LabVIEW sets the connector pane inputs and outputs of the selected VI to be the parameters configured in the HDL Interface Node Properties dialog box. The HDL Interface Node redefines the connector pane by replacing any controls and indicators you have already configured in the VI.
Delete Parameter—Deletes the selected input or output from the Parameters table.
Insert Parameter—Adds an input to the Parameters table. The input is a Boolean data type by default.

Code

Contains the following options:

Libraries—Lists the currently selected VHDL libraries for the HDL Interface Node. The libraries are available for the code entered in the text boxes below.
Add—Displays the Select a Library to Include dialog box. The Select a Library to Include dialog box adds a new VHDL library to the Libraries list.
Edit—Displays the Select a Library to Include dialog box. Use the Select a Library to Include dialog box to edit the library you select in the Libraries list.
Delete—Deletes the library you select in the Libraries list.
entity—Displays the name of the entity in the HDL.
is—Displays the parameters you define on the Parameters tab. You cannot edit the parameters in this text box. You must edit the parameters on the Parameters tab.
architecture implementation of hdlnode is—Contains text you enter for the signal declaration portion of the implementation in HDL. hdlnode appears in the name of this parameter as the name you enter in the entity field.
begin—Contains text you enter for the code of the implementation in HDL.
Check Syntax—Performs a syntax check of the HDL code in the above text boxes. If LabVIEW encounters errors in the HDL code, the Syntax Check Failed dialog box lists the errors. If LabVIEW does not encounter errors in the HDL code, a message informs you of syntactically correct HDL code.

Emulation

You can test the logic of an FPGA VI before compiling it by targeting an FPGA target emulator. If you want the HDL Interface Node to execute when you target an FPGA target emulator, you must create an emulation VI and add it to the HDL Interface Node Properties dialog box. If you do not create an emulation VI, the HDL Interface Node executes as an empty VI while the rest of the block diagram executes normally. Contains the following options:

Emulation VI—Changes or displays the currently selected emulation implementation of the HDL Interface Node. LabVIEW calls the VI you select from the HDL Interface Node and runs the VI as the implementation of the HDL Interface Node when you run the FPGA VI with an FPGA target emulator. Some targets might not support an emulator. Refer to the specific FPGA target hardware documentation for more information.
Emulation VI Absolute/Relative—Makes the currently selected emulation VI relative to the path to the owning FPGA VI of the HDL Interface Node or absolute to a specific path. If you do not save the owning FPGA VI to disk, you can use only absolute paths. If you save the owning VI to disk, you can use absolute or relative paths.
Browse—Displays the Choose Emulation VI dialog box. Browse to the location of the emulation VI for the HDL Interface Node.
Create Emulation VI—Displays the Export To VI dialog box. Select a VI from the Export To VI dialog box to which to export the HDL Interface Node parameters. LabVIEW sets the connector pane inputs and outputs of the selected VI to be the parameters configured in the HDL Interface Node Properties dialog box. The HDL Interface Node redefines the connector pane by replacing any controls and indicators you have already configured in the VI. You must define the parameters you need on the Parameters tab before you click the Create Emulation VI button. You must write LabVIEW code in the new VI that emulates the HDL code and runs in Windows. If you add or remove a parameter from the HDL Interface Node, click the Create Emulation VI button again and copy and paste the contents of the old emulation VI into the new emulation VI and rewire the block diagram and connector pane accordingly.

External Files

Contains the following options:

External Files—Displays the external files associated with the HDL Interface Node. LabVIEW copies the files to the LabVIEW FPGA Compile Server when you compile the VI. LabVIEW includes the external files in the final design created for the FPGA device.
Change Absolute/Relative—Makes the currently selected external file relative to the path to the owning FPGA VI of the HDL Interface Node or absolute to a specific path. If you do not save the owning FPGA VI to disk, you can use only absolute paths. If you save the owning VI to disk, you can use absolute or relative paths.
Add File—Displays the Add File dialog box. Use the Add File dialog box to navigate to the external file you want to add to the HDL Interface Node.
Remove File—Deletes the currently selected external file from the External Files list.

Execution Control

Contains the following options:

Single-Cycle Timed Loop—Contains the following options:
- Single-Cycle Timed Loop Not Allowed—Prevents you from using the HDL Interface Node in a single-cycle Timed Loop in an FPGA VI. If you select this option, you can use the HDL Interface Node only outside a single-cycle Timed Loop. If you place the HDL Interface Node in a single-cycle Timed Loop, LabVIEW returns a code generation error.
- Single-Cycle Timed Loop Allowed—Allows you to use the HDL Interface Node inside or outside a single-cycle Timed Loop. A generic entity on the Code page, InSingleCycle, indicates the position of the HDL Interface Node when you compile the VI for an FPGA target.
  Note The FPGA Module code generator updates the generic entity only at compile time, not during edit time.
- Single-Cycle Timed Loop Required—Requires you to use the HDL Interface Node in a single-cycle Timed Loop in an FPGA VI. If you do not place the HDL Interface Node in a single-cycle Timed Loop, the LabVIEW FPGA Compile Server returns an error when you try to compile the VI for an FPGA target.
Outputs Embed Shift Registers—Specifies that outputs of the HDL Interface Node must be wired to uninitialized shift registers in a single-cycle Timed Loop. The shift registers contain no logic but represent on the block diagram a shift register contained in the HDL Interface Node.

Simulation

Contains the following options:

Generate Enable Chain Testbench—Generates the shell of a testbench for testing the HDL code on the Code page in an HDL simulator. The testbench includes clk and enable_in. You must add code to the testbench shell to test the functionality you use in the HDL Interface Node.

After you generate the testbench, include the testbench and any external files in the HDL simulator.
Generate Single-Cycle Testbench—Generates a special testbench for an HDL simulator. The special testbench ensures the HDL code on the Code page meets the coding conventions necessary to work in a single-cycle Timed Loop.

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