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Asserts an interrupt on the interrupt line of the FPGA target. Support of interrupts and the number of interrupts available varies according to the FPGA target. Refer to the specific FPGA target hardware documentation for more information. The Interrupt VI communicates to the host VI that a specific logical interrupt has occurred. The Interrupt VI is a shared resource, so multiple uses of it induce additional delay and jitter due to arbitration. To handle the interrupts in the host VI, use the Wait on IRQ and Acknowledge IRQ methods in the Invoke Method function.

	IRQ Number specifies which logical interrupt to assert. The default is 0.
	Wait Until Cleared specifies if this VI waits until the host VI acknowledges the logical interrupt or this VI asserts the interrupt and continues. Set this parameter to TRUE if you want the VI to wait until the host VI acknowledges it. Set this parameter to FALSE if you do not want the VI to wait. The default is FALSE.
	Error indicates whether an error occurred.