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Invokes an method on an I/O item or hardware under an FPGA target in the Project Explorer window, such as a C Series module. A method can have zero or more parameters. The methods available vary according FPGA target, configuration, and I/O resource. Also, FPGA targets do not support the use of certain methods in a single-cycle Timed Loop. Refer to the specific FPGA target hardware documentation for more information. You must configure the FPGA I/O Method Node with the FPGA I/O item before you select a method from the shortcut menu.

This node replaces the functionality of the Digital Data and Digital Enable functions from the FPGA Module 1.x. Details  

FPGA I/O Method Node Details

FPGA targets typically support the following methods for I/O items that correspond to bidirectional digital I/O lines and ports. Support varies by FPGA target and I/O resource.

• Set Output Data Method—Writes data to the digital line or port without enabling the line or port. You can use the Set Output Enable method to enable output. The data type of the Data input depends on the I/O item. For example, if the I/O item is a digital line, Data requires a Boolean data type.
• Set Output Enable Method—Enables output on the digital line or port. You can use the Set Output Data method to control the state of the output lines. The data type of the Enable input depends on the I/O item. For example, if the I/O item is a digital line, Enable requires a Boolean data type.

You can right-click the FPGA I/O Method Node on the block diagram and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. If an error occurs, you might receive incorrect data. Add error terminals to be sure the data you receive is valid. FPGA targets might report errors differently. Refer to the specific FPGA target hardware documentation for information about how specific FPGA targets report errors.

Note  Adding error in and error out parameters increases the amount of space the function uses on the FPGA target. The error in and error out parameters also can cause slower execution on the FPGA target.