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Reads from memory available on the FPGA target. Use the Memory Read function in conjunction with the Memory Write function. Details  

Address specifies the location of the data in memory on the FPGA target. The valid address range depends on the Depth you specify in the Memory Properties dialog box. For example, if you specify a Depth of 1000, the valid address range is 0–999. If Address exceeds the address range, the data is undefined. Add error terminals so LabVIEW can notify you if Address exceeds the address range. Right-click the function on the block diagram and select Show Error Terminals from the shortcut menu to add standard LabVIEW error in and error out parameters to the function. Note  Adding error in and error out parameters increases the amount of space the function uses on the FPGA target. The error in and error out parameters also can cause slower execution on the FPGA target.

Data is the data read from memory on the FPGA target. Data is directly accessible only from within the FPGA VI. You cannot directly access the data in the memory of the FPGA target from the host VI. You must use controls, indicators, or DMA FIFOs to access data from the host VI. The Data data type is the data type you configure in the Memory Properties dialog box when you create the memory item. If you do not initialize the memory item, the data is undefined.

Memory Read Details

To read from or write to the FPGA memory with the Memory Read and Memory Write functions, you must create memory items. You can create a memory item in the Project Explorer window or using a VI-Scoped Memory Configuration node. You then can right-click the Memory Read or Memory Write function and select the memory item from the Select Memory shortcut menu.

Tip  You can click a memory item in the Project Explorer window and drag it onto the block diagram to place a Memory Read function on the block diagram.

Right-click the Memory Read function and select Add New Memory from the shortcut menu to create a new target-scoped memory item.

If you reset the FPGA VI, the memory remains unchanged. You must download the FPGA VI again to reinitialize the memory.

Special Considerations for Single-Cycle Timed Loops

If you use the Memory Read function in a single-cycle Timed Loop, you must set the Read option in the Memory Properties dialog box to Arbitrate if Multiple Requestors Only or Never Arbitrate for the memory item, and you cannot use this function with the same memory item anywhere else in the FPGA VI.

If you use the Memory Read function in a single-cycle Timed Loop, wire the output directly to an uninitialized shift register or feedback node.

The Memory Read function takes an entire clock cycle to execute. You cannot use memory to transfer data among multiple clock domains.