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You can control and monitor data directly from the FPGA target using Interactive Front Panel Communication. You also can use a host VI running on the host computer or on an RT target to control or monitor the FPGA VI through Programmatic FPGA Interface Communication. With Interactive Front Panel Communication, you can use a polling-based method of communicating between the host VI and the FPGA VI by reading and writing indicators and controls. With Programmatic FPGA Interface Communication, you can use an interrupt-based method of communication where, in addition to communicating using indicators and controls, the FPGA VI can generate hardware interrupts that the host VI can wait for and acknowledge. You can use FPGA Interface functions to create host VIs that communicate with FPGA VIs.

A host VI can control and monitor only data passed through the FPGA VI front panel window. For example, if you want the host VI to monitor the data from an analog input terminal, you must wire an indicator to an FPGA I/O Node configured with an analog input resource on the FPGA VI block diagram.

Interrupt-Based Communication

You can use interrupts to notify the host VI of events, such as data being ready, an error occurring, or a task finishing. An interrupt is a physical hardware line to the host that the FPGA target asserts.

Use the Interrupt VI in FPGA VIs to generate any of the 32 independent logical interrupts available on the FPGA target. Each logical interrupt specifies the reason for causing the interrupt and allows you to handle it differently in software. You can set the Interrupt VI to wait until the host VI acknowledges the interrupt on the FPGA target by wiring the Wait Until Cleared input. In this case, the Interrupt VI waits until the host VI controlling the device acknowledges the interrupt.

Use caution when you include simultaneous interrupt calls on the FPGA target. The interrupt becomes a shared resource if you use more than one, and you can induce jitter.

The advantage of using interrupt-based communication instead of polling-based communication is that the host VI can perform other operations while waiting for the interrupt. In contrast, if the host VI uses polling-based communication, the host VI does not have time to perform other operations while waiting for a specific data value from the FPGA target.

Direct Memory Access Communication

You can use Direct Memory Access (DMA) FIFOs to transfer data between the FPGA VI and host VI. A FIFO is an array of memory elements in which the first element you write to the array is the first element you read from it. Use DMA FIFOs to stream large amounts of data to and from the host VI.

Note  Support of DMA FIFOs varies by FPGA target. Refer to the specific FPGA target hardware documentation for more information.

An advantage of DMA FIFOs is that the host computer processor can perform calculations while the FPGA target transfers data to the host computer memory. FPGA targets that support DMA FIFOs have direct access to write to memory on the host computer without involving the host computer processor. Without DMA, you can transfer data only through the host computer processor. LabVIEW performs DMA transfers through bus mastering. FPGA targets that support DMA FIFOs can master the PCI bus. The FPGA target controls the PCI bus and accesses memory directly without needing to access the host processor.

DMA FIFOs include one endpoint on the host computer and one endpoint on the FPGA target. The FPGA VI writes the FIFO one element at a time with the FIFO Write function or reads the FIFO one element at a time with the FIFO Read function. The host VI reads from or writes to the FIFO one or more elements at a time with the Invoke Method function.

A DMA FIFO consists of two parts, an FPGA part and a host computer part. The FPGA part of the DMA FIFO is stored in memory on the FPGA. The host computer part of the DMA FIFO is stored in memory on the host computer. LabVIEW uses a DMA Engine to connect the two parts. The DMA Engine includes driver software and hardware logic. When the DMA Engine runs, it transfers data between the two parts of the FIFO automatically so they act as one FIFO array.

DMA FIFOs support the U32 integer data type. If you want to transfer a different data type, convert the data type to a series of U32 data types, transfer it, and then reconstitute the data in the host VI.

Specifying DMA FIFO Depth

When you create a FIFO, you specify the size of the FPGA part of the FIFO, or depth. You also can specify the size of the host computer part of the FIFO in a host VI with the Invoke Method function configured with the Configure method. If you do not specify the size of the host computer part of the FIFO in the host VI, the host computer part size is twice the size of the FPGA part of the FIFO. Make sure the host computer and FPGA parts of the FIFO are large enough so that they do not fill in the case of the largest delay in the host VI. For example, PCI bus traffic can cause delays in automatic transfers from the FPGA target to the host. Typically, the faster the transfer rate, the more depth you need.

Consider the following situations when you specify the depth of the DMA FIFO:

• FIFO depth is too small—When a large transfer delay occurs, the FPGA target cannot transfer the data immediately to the host part of the FIFO before the FPGA part of the FIFO fills. The Full output of the FIFO Write function returns TRUE to indicate that the FIFO is full and that it cannot write data to the DMA FIFO. If the host part of the FIFO is too small, the FPGA target empties the FIFO before you can write to it again.
• FIFO depth is too large—If the FPGA part of the DMA FIFO is too large, other functions cannot use the memory of the FIFO not being used. If the host part of the FIFO is too large, other programs on the host computer cannot use the unused memory in the DMA FIFO.

Determining the Status of a DMA FIFO

You can use one of the following three methods to determine the status of a DMA FIFO:

• Blocking—In the host VI, wire the amount of data you want to read from the DMA FIFO to the Number of Elements input of the Invoke Method function configured with the Read method. The DMA Engine attempts to complete the transfer within the amount of time you specify with the Timeout input of the Invoke Method function configured with the Read method. The DMA Engine does not yield control of the CPU in order to achieve maximum throughput.
• Interrupts—Use an Interrupt VI in the FPGA VI to notify the host VI when data is available. This method uses the least amount of CPU overhead.
• Polling—In the host VI, wire a constant of zero to the Number of Elements input of the Invoke Method function configured with the Read method. The Read method returns immediately and the Elements Remaining output returns the number of elements that you can read in a subsequent call to the Read method. This method gives you control over how often polling occurs.