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To interface the HDL code to the rest of the block diagram, you must define inputs and outputs for the HDL Interface Node. Begin configuring the HDL Interface Node by defining the parameters of the node on the Parameters tab of the HDL Interface Node Properties dialog box.

To configure a parameter, double-click a cell in the Name column of the Parameters table and enter the name of the parameter. The Name you enter corresponds to a port name in the HDL code. The Name appears as the parameter name on the terminal on the block diagram. Click the other cells to select the Direction, Type, and if the parameter is a Boolean array data type, the Length of the parameter. The HDL code for the parameter appears as a port in the hdlnode entity on the Code tab. You can use the Import from VI and Export to VI buttons on the Parameters tab to copy connector pane parameters between the HDL Interface Node and other VIs. You then can reuse the same inputs and outputs without defining each parameter more than once—once in the HDL Interface Node and once for each of the other VIs.

Note  If you wire a Boolean array into an HDL Interface Node, element zero in the Boolean array maps to element n in the vector. The std_logic vector is described as n down to zero, where n is the number of elements - 1.