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LabVIEW and the LabVIEW FPGA Module follow a dataflow model for running VIs. A block diagram node only executes when all its inputs are available. When a node completes execution, it supplies data to its output terminals and passes the output data to the next node in the dataflow path. The HDL Interface Node uses an enable chain to follow the LabVIEW dataflow model. The enable chain is the collection of signals and an associated protocol for controlling data flow of inputs and outputs of the HDL components. The HDL Interface Node includes the following execution control and enable chain signals as default ports, listed on the Code tab.

Execution Control Inputs

• clk—The clock signal supplied to the FPGA. You can use the clk input to clock the HDL code.
• reset—The signal asserted by LabVIEW at the beginning of execution, before the top-level VI runs or when you load the top-level VI from flash memory and run it. You can use the reset signal to initialize flip-flops in the HDL code that you want initialized when the VI runs. LabVIEW asserts the reset signal for at least one clock cycle.

Enable Chain Inputs

• enable_in—The signal LabVIEW asserts when all inputs wired to the HDL Interface Node are valid. LabVIEW asserts enable_in when all the nodes before the HDL Interface Node in the data flow finish executing. You can monitor enable_in to know when the HDL code can start executing.
• enable_clr—The signal the VI or loop asserts to indicate to the subVIs or nodes, including HDL Interface Nodes, in the VI or loop that they must deassert enable_out on the next rising edge of clk. In loops other than the single-cycle Timed Loop, enable_clr asserts after each loop iteration is complete and before the next iteration begins. If you use a single-cycle Timed Loop, the VI or loop does not assert enable_clr.

Enable Chain Output

• enable_out—Assert this signal in the HDL code when you want to indicate to the block diagram that the HDL code is complete and to signal to subsequent functions in the data flow to execute.

The HDL code you include in the FPGA VI must fit into LabVIEW dataflow execution semantics by properly controlling the enable chain. If you do not properly control the enable chain, the HDL Interface Node might disrupt the execution of the other nodes on the block diagram. Use the Generate Enable Chain Testbench option on the Simulation tab of the HDL Interface Node Properties dialog box to test the enable chain.