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You can define the functionality of the HDL Interface Node using HDL code in the implementation section of the Code tab in the HDL Interface Node Properties dialog box. However, you also might want to include external HDL code, such as external intellectual property, in the functionality of the HDL Interface Node. Use the External Files tab to reference external HDL code. You also can reference netlist files, such as EDIF files, or any other file used during the Xilinx compile process.

Note  If you add a netlist file, you must disable the automatic I/O buffer insertion. By default, if you create a netlist file using Xilinx ISE, the file includes I/O buffers. However, the I/O buffers cause errors in the Xilinx compiler.

If you use external HDL code, you must include HDL code on the Code tab to interface with the external file. You also must have execution control and enable chain logic. You can place the execution control and enable chain logic on the Code tab, in the external file, or partially in both.

On the External Files tab, click the Add File button to display the Add File dialog box. Browse to the file you want to add. You can add multiple external files. Click the Change Absolute/Relative button if the external files are in the same directory or a lower subdirectory as the FPGA VI where you use the HDL Interface Node and you want to use paths relative to the location of the FPGA VI.

Note  If you do not save the owning FPGA VI to disk, you can use only absolute paths. If you save the owning VI to disk, you can use absolute or relative paths.