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Use the single-cycle Timed Loop in an FPGA VI to execute code in one clock cycle of the default FPGA target clock or at a rate you specify. For example, you can optimize a digital event counter application by using the single-cycle Timed Loop, as shown in the following figure.

Implementing Multiple Clock Domains with the Single-Cycle Timed Loop

As the longest path through the logic inside the single-cycle Timed Loop increases, the maximum clock rate decreases. You can pipeline long combinatorial paths by inserting shift registers to keep the final maximum clock rate high. You also can separate sections of independent logic into different clock domains. You then can use long combinatorial paths in a slow clock domain and short combinatorial paths in a fast clock domain. Fast clock domains are ideal for operations requiring fast reaction time or higher resolution on measurements such as pulse width or event counts.

Specify clock domains in FPGA VIs using the single-cycle Timed Loop. All available FPGA target clocks appear in the Project Explorer window as FPGA target base or derived clocks. You can select any FPGA target base or derived clock that the FPGA target supports as the clock for the single-cycle Timed Loop.

Transferring Data among Multiple Clock Domains

You might need to transfer data between single-cycle Timed Loops set to run under different clock domains. Digital inputs on most FPGA targets are asynchronous to the top-level FPGA target clock and must be resynchronized. Some FPGA targets allow you to use external clocks or I/O specially synchronized to an onboard clock. Data on digital inputs or other I/O types might be synchronous to the top-level FPGA target clock and so you can avoid the resynchronization overhead. Refer to the specific FPGA target hardware documentation for information about the synchronicity of available I/O.

You can use one of the following methods to transfer data among clock domains:

• Local or global variables—You can write to a local or global variable from a maximum of one clock domain. You then can read from the local or global variable in as many clock domains as you need. LabVIEW uses handshaking to transfer data from the writing domain to the reading domains. You must wait several clock cycles of both the source and destination to handshake a new value. Some values you write from one clock domain might not be read by the destination domain because of the handshaking overhead. To consistently read data, place data in a cluster.
• FIFOs—You can write data into a target-scoped or VI-scoped FIFO from a maximum of one clock domain. You then can read the FIFO from a maximum of one clock domain. LabVIEW can read all data you write to the FIFO when the FIFO is not full.
• Single-cycle Timed Loop tunnels—You can wire input signals to the single-cycle Timed Loop. LabVIEW handshakes input signals to the loop clock domain. After the single-cycle Timed Loop terminates, LabVIEW handshakes any output signals to the top-level FPGA target clock.

LabVIEW returns the Code Generation Errors window if you try to transfer data among multiple clock domains not using one of the above methods.