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In addition to providing the I/O capabilities, the FPGA Module enables you to use the LabVIEW VIs and functions appropriate for FPGA targets.

Restricted and Unavailable VIs and Functions

Some LabVIEW VIs and functions are not available or have restrictions in FPGA VIs.

The following LabVIEW features are not available for FPGA VIs:

• Floating-point functions
• Variable-size and multidimensional arrays
• Math and Signal Processing VIs not specific to the FPGA Module
• ActiveX
• Dialog boxes
• File I/O
• Printing
• Programmatic menus
• VI Server
• VI Server properties and methods

Support for other LabVIEW features varies by target. Refer to the specific FPGA target hardware documentation for information about supported LabVIEW features.

Mathematical Operations

The FPGA Module restricts the use of mathematical operations in FPGA VIs to integer numeric data types. You can perform integer math using the Numeric functions. You also can perform more advanced integer math, analysis, and control operations using the FPGA Math & Analysis VIs. You cannot use floating-point operations in FPGA VIs.

When you perform integer math, the results might overflow. Integer overflow occurs when the result of a mathematical operation exceeds the range of the output data type. For example, the range of a U8 integer is 0 to 255. Adding two U8 integers together that have a result greater than 255 results in overflow, such as 200 + 70. When overflow occurs, the result rolls over, or wraps, at the limit of the range and the result modulo 256 is returned. For example, a result of 270 for a U8 integer wraps at 256 and returns 14.

You can take advantage of the rollover behavior that occurs with overflow in some applications. For example, the execution time measurement example relies on the rollover behavior of overflow for proper operation. The example configures the Tick Count Express VIs with an 8-bit Size of Internal Counter and milliseconds for Counter Units. When the internal counter of the Tick Count Express VI reaches 255 ms, it rolls over to 0. If the first Tick Count Express VI returns a Tick Count of 132 ms and the execution time of the LabVIEW code to be measured takes 140 ms, the internal counter has rolled over and the second Tick Count Express VI returns a Tick Count value of 16 ms. When the block diagram subtracts 132 from 16, overflow occurs and results in the value of 140.

Note  The Tick Count Express VI takes a single cycle to execute. In this example, if you set Counter Units as Ticks instead of mSec, the returned result from the subtraction is 141 even though the LabVIEW code in the middle sequence takes only 140 ticks to execute.

If you want to avoid integer overflow, you can use the Scale By Power Of 2 function to reduce the magnitude of the inputs, use a larger output data type, or use Saturation Arithmetic VIs. If you use the Scale By Power Of 2 function, you minimize the amount of space you use on the FPGA target to handle saturation. However, you lose precision and you also must carefully program the FPGA VI to be sure you scale all inputs and outputs correctly. If you use a larger output data type, you take up more space on the FPGA target but you can program the FPGA VI more quickly and easily and receive more accurate data. You can use the Saturation Arithmetic VIs instead of other Numeric functions and select a larger output type with the original input types, often resulting in more efficient code in the FPGA VI.

Tip  Use the smallest data type possible in FPGA VIs to minimize the space you use on the FPGA.

If you want to allow overflow, you can use the Saturation Arithmetic VIs to handle overflow if it occurs. You can saturate or wrap the result and show the overflow terminal in the configuration dialog box of each Saturation Arithmetic VI. Choose the Saturate option to minimize error if overflow occurs and to avoid discontinuities in the signal. Choose the Wrap option to use the smallest amount of space on the FPGA target. You also can use the Numeric functions to implement the wrapping overflow mode.

Tip  To save space on the FPGA, use the Wrap option in Saturation Arithmetic VIs when possible. You then can use the overflow parameter to indicate when a particular result has overflowed.

You can configure the Saturation Arithmetic VIs to handle signed or unsigned integer overflow. You also can configure the Saturation Arithmetic VIs to return a maximum or minimum value if an overflow condition occurs instead of performing modular arithmetic.

Arrays

You can use only fixed-size, one-dimensional arrays in FPGA VIs. You can make any array constant, control, or indicator fixed-size by right-clicking the array index and selecting Set Dimension Size from the shortcut menu.

You cannot use an array function that returns a variable-size array. However, if you use appropriate constants with many array functions, the resulting array is fixed-size. For example, if you use the Array Subset function, you must wire constants to the index and length parameters so that the resulting subarray is fixed-size.

Tip  Arrays consume significant amounts of space on the FPGA. To optimize the FPGA VI, avoid using arrays larger than 32 elements.

Memory

You can use FPGA memory for data storage in the FPGA VI. You access the FPGA memory using the Memory Read and Memory Write functions configured for a memory item. You can access all available memory on the FPGA using memory items. Each memory item is different and contains an independent address. You can use the memory items with the Memory Read and Memory Write functions to perform basic read and write operations on the FPGA memory and as building blocks to create more advanced memory functions such as FIFOs, dual-ported memory, look-up tables, and so on.

You can create look-up tables with constant or variable entries in FPGA VIs. You can use fixed-size arrays for smaller look-up tables with variable entries. You can use constant fixed-size arrays when the look-up table entries do not need to change and you want to limit FPGA usage. For larger look-up tables or look-up tables that require interpolation, use the Look-Up Table 1D Express VI available with the FPGA Module.

Memory functions and look-up tables contain embedded shift registers, which means the outputs always correspond to the inputs on the previous clock cycle. If you use an object with an embedded shift register outside a single-cycle Timed Loop, the FPGA Module compensates by postponing dataflow execution. However, if you use an object with an embedded shift register in a single-cycle Timed Loop, the FPGA Module does not postpone execution, so you must wire the outputs for the object directly to an uninitialized shift register. You cannot wire the outputs to another object.

Using HDL Code in FPGA VIs

You can use the FPGA Module to rapidly prototype and develop hardware in the same intuitive programming environment you use to develop software applications. However, you might have algorithms or applications in a text-based hardware description language (HDL) that you want to use in FPGA VIs without rewriting the code in LabVIEW. If you have a block of HDL code you want to use in an FPGA VI, you can enter the code in the HDL Interface Node rather than rewriting the code in LabVIEW.