Writing HDL Code to Adapt to Multiple Clock Rates (FPGA Module)

LabVIEW FPGA Module 8.2 Help
August 2006

NI Part Number:
371599B-01

»View Product Info

The HDL Interface Node includes a generic that allows different hardware implementations to be generated based on the value of the clock rate. The code for the ports and the generic appears in the hdlnode entity on the Code tab.

Use the ClockFrequency generic to generate statements in the HDL code based on the value of ClockFrequency. You can generate different HDL code based on the frequency you use to compile the design. For example, you might need a pulse to be 50 nanoseconds long. If the clock rate is 40 MHz, you generate a 2-cycle pulse. If the clock rate is 80 MHz, you generate a 4-cycle pulse. The following VHDL code demonstrates using the ClockFrequency generic to determine the pulse.

if ClockFrequency = 40000000
  generate -- add code to generate 2-cycle pulse
  end generate;
if ClockFrequency = 80000000
  generate -- add code to generate 4-cycle pulse
end generate;

LabVIEW passes the actual value of the ClockFrequency generic to the HDL code when you compile the VI. Configure the default clock rate in the Top-Level Clock page of the FPGA Target Properties dialog box. You also can change the clock rate for a single-cycle Timed Loop within an FPGA VI by double-clicking the Input Node and selecting a clock rate in the Configure Timed Loop dialog box.

Note The HDL Interface Node updates the ClockFrequency generic to match the current clock domain in which the node is instantiated. If you include the HDL Interface Node in a subVI that is instantiated in multiple clock domains, the ClockFrequency generic lists only one of the frequencies on the Code tab.

Writing HDL Code to Adapt to Multiple Clock Rates (FPGA Module)

Resources