Importing HDL Code into FPGA VIs (FPGA Module)
If you have a block of HDL code you want to use in an FPGA VI, you can use the HDL Interface Node rather than rewriting the code in LabVIEW. You enter all the parameters and the HDL code in the HDL Interface Node Properties dialog box. The parameters become terminals on the HDL Interface Node. You then wire the parameters as you do any VI or function on the block diagram.
 |
Note Do not use the HDL Interface Node if you are not already familiar with an HDL programming language. |
When you first place the HDL Interface Node on the block diagram of an FPGA VI, the node has no inputs, outputs, or defined functionality. Double-click the node to display the HDL Interface Node Properties dialog box. Use the HDL Interface Node Properties dialog box to configure inputs, outputs, internal functionality, external reference files, and so on. You can write HDL code to run in While Loops, single-cycle Timed Loops, or anywhere on the block diagram. You can configure the HDL Interface Node to use a separate emulation VI if you target an FPGA target emulator. You also can generate test benches to use in HDL simulators that test the functionality of the HDL component.
You cannot access I/O resources in the HDL code. If the HDL code needs to access I/O resources, you must create parameters for the input and output signals. You then can wire the parameters on the HDL Interface Node to FPGA I/O functions.
You can enter the HDL code directly into the Code tab of the HDL Interface Node Properties dialog box. You can verify the syntax of the HDL code you enter by clicking the Check Syntax button.
|
Note LabVIEW currently supports VHDL in the HDL Interface Node. To use Verilog or another hardware design language, first compile the files to an EDIF or NGC netlist. You then can attach the netlist file to the HDL Interface Node on the External Files tab of the HDL Interface Node Properties dialog box and interface to the netlist file with HDL code on the Code tab. |
Resources
E-Mail this Page