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Jitter occurs if a requestor in a loop is delayed in becoming an accessor due to resource contention with one or more additional requestors and the delay varies per loop iteration. For example, you might have an application performing a timed While Loop that samples analog input at a fixed rate. Each time the FPGA I/O Node executes, the node becomes an accessor as soon as it requests the analog input resource. If you add a second timed While Loop that samples the same analog input resource, the two FPGA I/O Nodes might simultaneously request the analog input resource. In this case, the arbiter delays one of the requestors while allowing the other requestor to become an accessor. The delayed requestor has jitter because the access does not occur immediately after the request was made.

To avoid jitter, design the FPGA VI block diagram to make sure a requestor does not access the shared resource when the shared resource is busy or to make sure two requests do not occur during the same clock cycle. Jitter occurs most often when you have a shared local variable with multiple writers or a shared subVI from two independently running loops or unrelated parts of the VI, as shown in the following figure.

The VI in the figure above shows two While Loops that might attempt to write to the Edge Detected local variable simultaneously. The arbiter allows one While Loop to access Edge Detected at a time. The other While Loop does not access Edge Detected until after the first While Loop finishes. Jitter is introduced into the delayed While Loop.

The possibility of jitter grows with the number of accessors. If you do not schedule simultaneous requests, the delay through the arbiter is constant regardless of the number of potential accessors.