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If you want to optimize the performance of an FPGA VI, you might be able to modify the FPGA VI to increase speed, consume less space, or both. The following table includes techniques you might want to consider to optimize an FPGA VI.

Optimization Technique	FPGA Speed	FPGA Size
Reduce combinatorial paths.
Use single-cycle Timed Loops.
Use parallel operations.
Select an appropriate arbitration option.
Use non-reentrant subVIs.
Use reentrant subVIs.
Limit the number of front panel objects, such as arrays.
Use the smallest data type possible.
Avoid large VIs and functions, if possible.